參數(shù)資料
型號: Alpha 21164
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Alpha Microprocessor(64位微處理器)
中文描述: 阿爾法微處理器(64位微處理器)
文件頁數(shù): 8/115頁
文件大?。?/td> 846K
代理商: ALPHA 21164
8
Microarchitecture
Memory Address Translation Unit
3.4.1 Data Translation Buffer
The 64-entry, fully associative, dual-read-ported data translation buffer (DTB) stores
recently used data stream (Dstream) page table entries (PTEs). Each entry supports
all four granularity hint-bit combinations, so that a single DTB entry can provide
translation for up to 512 contiguously mapped, 8KB pages.
The DTB also supports the register-enabled superpage extension. The DTB super-
page maps provide virtual-to-physical address translation for two regions of the vir-
tual address space.
3.4.2 Miss Address File
The MTU begins the execution of each load instruction by translating the virtual
address and by accessing the data cache (Dcache). Translation and Dcache tag read
operations occur in parallel. If the addressed location is found in the Dcache (a hit),
then the data from the Dcache is formatted and written to either the integer register
file (IRF) or floating-point register file (FRF). The formatting required depends on
the particular load instruction executed. If the data is not found in the Dcache (a
miss), then the address, target register number, and formatting information are
entered in the miss address file (MAF).
The MAF performs a load-merging function. When a load miss occurs, each MAF
entry is checked to see if it contains a load miss that addresses the same Dcache (32-
byte) block. If it does, and certain merging rules are satisfied, then the new load miss
is merged with an existing MAF entry. This allows the MTU to service two or more
load misses with one data fill from the CBU.
There are six MAF entries for load misses and four more for IDU instruction fetches
and prefetches. Load misses are usually the highest MTU priority.
3.4.3 Store Execution
The Dcache follows a write-through protocol. During the execution of a store
instruction, the MTU probes the Dcache to determine whether the location to be
overwritten is currently cached. If so (a Dcache hit), the Dcache is updated. Regard-
less of the Dcache state, the MTU forwards the data to the CBU.
A load instruction that is issued one cycle after a store instruction in the pipeline cre-
ates a conflict if both the load and store operations access the same memory location.
(The store instruction has not yet updated the location when the load instruction
reads it.) This conflict is handled by forcing the load instruction to take a replay trap;
that is, the IDU flushes the pipeline and restarts execution from the load instruction.
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