參數(shù)資料
型號： Alpha 21164
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Alpha Microprocessor(64位微處理器)
中文描述： 阿爾法微處理器（64位微處理器）
文件頁數(shù)： 82/115頁
文件大?。?/td> 846K
代理商： ALPHA 21164
82
Electrical Data
Clocking Scheme
11.3 Clocking Scheme
Note:
The preferred clock mode of the 21164 is 1×. This is a change from the
earlier versions of the 21164, which had a preferred clock mode of 2×.
Refer to Section 11.4.8 for more details.
The differential input clock signals
osc_clk_in_h,l
run at the internal frequency of
the time base for the 21164. The output signal
cpu_clk_out_h
toggles with an
unspecified propagation delay relative to the transitions on
osc_clk_in_h,l
.
System designers have a choice of two system clocking schemes to run the 21164
synchronous to the system:
1.
The 21164 generates and drives out a system clock,
sys_clk_out1_h,l
. It runs
synchronous to the internal clock at a selected ratio of the internal clock fre-
quency. There is a small clock skew between the internal clock and
sys_clk_out1_h,l
.
The 21164 synchronizes to a system clock,
ref_clk_in_h
, supplied by the sys-
tem. The
ref_clk_in_h
clock runs at a selected ratio of the 21164 internal clock
frequency. The internal clock is synchronized to the reference clock by an onchip
digital phase-locked loop (DPLL).
2.
11.3.1 Input Clocks
The differential input clocks
osc_clk_in_h,l
provide the time base for the chip when
dc_ok_h
is asserted. These pins are self-biasing, and must be capacitively coupled to
the clock source on the module.
Note:
It is not desirable to drive the
osc_clk_in_h,l
pins directly. This is a
change from earlier versions of the 21164.
The terminations on these signals are designed to be compatible with system oscilla-
tors of arbitrary dc bias. The oscillator must have a duty cycle of 60%/40% or tighter.
Figure 13 shows the input network and the schematic equivalent of
osc_clk_in_h,l
terminations.
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