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參數(shù)資料
| 型號(hào)： | Alpha 21164 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Alpha Microprocessor(64位微處理器) |
| 中文描述： | 阿爾法微處理器（64位微處理器） |
| 文件頁(yè)數(shù)： | 52/115頁(yè) |
| 文件大?。?/td> | 846K |
| 代理商： | ALPHA 21164 |
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52
IEEE Floating-Point Conformance
7 IEEE Floating-Point Conformance
The 21164 supports the IEEE floating-point operations as defined by the Alpha
architecture. Support for a complete implementation of the IEEE
Standard for
Binary Floating-Point Arithmetic
(ANSI/IEEE Standard 754 1985) is provided by a
combination of hardware and software as described in the
Alpha Architecture
Reference Manual
.
Additional information about writing code to support precise exception handling
(necessary for complete conformance to the standard) is in the
Alpha Architecture
Reference Manual.
The following information is specific to the 21164:
Invalid operation (INV)
The invalid operation trap is always enabled. If the trap occurs, then the destina-
tion register is UNPREDICTABLE. This exception is signaled if any VAX
architecture operand is nonfinite (reserved operand or dirty zero) and the opera-
tion can take an exception (that is, certain instructions, such as CPYS, never take
an exception). This exception is signaled if any IEEE operand is nonfinite
(NAN, INF, denorm) and the operation can take an exception. This trap is also
signaled for an IEEE format divide of ±0 divided by ±0. If the exception occurs,
then FPCR<INV> is set and the trap is signaled to the IDU.
Divide-by-zero (DZE)
The divide-by-zero trap is always enabled. If the trap occurs, then the destination
register is UNPREDICTABLE. For VAX architecture format, this exception is
signaled whenever the numerator is valid and the denominator is zero. For IEEE
format, this exception is signaled whenever the numerator is valid and nonzero,
with a denominator of ±0. If the exception occurs, then FPCR<DZE> is set and
the trap is signaled to the IDU.
For IEEE format divides, 0/0 signals INV, not DZE.
Floating overflow (OVF)
The floating overflow trap is always enabled. If the trap occurs, then the destina-
tion register is UNPREDICTABLE. The exception is signaled if the rounded
result exceeds in magnitude the largest finite number, which can be represented
by the destination format. This applies only to operations whose destination is a
floating-point data type. If the exception occurs, then FPCR<OVF> is set and the
trap is signaled to the IDU.
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