參數(shù)資料
型號: Alpha 21164
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Alpha Microprocessor(64位微處理器)
中文描述: 阿爾法微處理器(64位微處理器)
文件頁數(shù): 49/115頁
文件大?。?/td> 846K
代理商: ALPHA 21164
Alpha Architecture Basics
49
The Architecture
6 Alpha Architecture Basics
This section provides some basic information about the Alpha architecture. For more
detailed information about the Alpha architecture, see the
Alpha Architecture Refer-
ence Manual
.
6.1 The Architecture
The Alpha architecture is a 64-bit load and store RISC architecture designed with
particular emphasis on speed, multiple instruction issue, multiple processors, and
software migration from many operating systems.
All registers are 64 bits long and all operations are performed between 64-bit regis-
ters. All instructions are 32 bits long. Memory operations are either load or store
operations. All data manipulation is done between registers.
The Alpha architecture supports the following data types:
8-, 16-, 32-, and 64-bit integers
IEEE 32-bit and 64-bit floating-point formats
VAX architecture 32-bit and 64-bit floating-point formats
In the Alpha architecture, instructions interact with each other only by one instruc-
tion writing to a register or memory location and another instruction reading from
that register or memory location. This use of resources makes it easy to build imple-
mentations that issue multiple instructions every CPU cycle.
The 21164 uses a set of subroutines, called privileged architecture library code
(PALcode), that is specific to a particular Alpha operating system implementation
and hardware platform. These subroutines provide operating system primitives for
context switching, interrupts, exceptions, and memory management. These subrou-
tines can be invoked by hardware or CALL_PAL instructions. CALL_PAL instruc-
tions use the function field of the instruction to vector to a specified subroutine.
PALcode is written in standard machine code with some implementation-specific
extensions to provide direct access to low-level hardware functions. PALcode sup-
ports optimizations for multiple operating systems, flexible memory-management
implementations, and multi-instruction atomic sequences.
The Alpha architecture performs byte shifting and masking with normal 64-bit, reg-
ister-to-register instructions and performs single-byte load and store instructions if
they are enabled by bit <17> of the ICSR.
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