參數(shù)資料
型號： Alpha 21164
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Alpha Microprocessor(64位微處理器)
中文描述： 阿爾法微處理器（64位微處理器）
文件頁數(shù)： 5/115頁
文件大?。?/td> 846K
代理商： ALPHA 21164
Microarchitecture
5
Instruction Fetch/Decode and Branch Unit
3.1 Instruction Fetch/Decode and Branch Unit
The primary function of the instruction fetch/decode and branch unit (IDU) is to
manage and issue instructions to the IEU, MTU, and FPU. It also manages the
instruction cache. The IDU contains:
Prefetcher and instruction buffer
Instruction slot and issue logic
Program counter (PC) and branch prediction logic
48-entry instruction translation buffers (ITBs)
Abort logic
Register conflict logic
Interrupt and exception logic
3.1.1 Instruction Prefetch and Decode
The IDU handles only NATURALLY ALIGNED groups of four instructions
instructions in a group are issued. If a branch to the middle of an INT16 group
occurs, then the IDU attempts to issue the instructions from the branch target to the
end of the current INT16; the IDU then proceeds to the next INT16 of instructions
after all the instructions in the target INT16 are issued. Thus, proper code scheduling
is required to achieve optimal performance.
3.1.2 Branch Prediction
The branch unit, or prediction logic, is also part of the IDU. Branch and PC predic-
tion are necessary to predict and begin fetching the target instruction stream before
the branch or jump instruction is issued. Each instruction location in the instruction
cache (Icache) contains a 2-bit history state to record the outcome of branch instruc-
tions.
3.1.3 Instruction Translation Buffer
The IDU includes a 48-entry, fully associative instruction translation buffer (ITB).
The buffer stores recently used instruction stream (Istream) address translations and
protection information for pages ranging from 8KB to 512KB and uses a not-last-
used replacement algorithm.
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