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參數(shù)資料
| 型號(hào)： | Alpha 21164 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Alpha Microprocessor(64位微處理器) |
| 中文描述： | 阿爾法微處理器（64位微處理器） |
| 文件頁(yè)數(shù)： | 10/115頁(yè) |
| 文件大?。?/td> | 846K |
| 代理商： | ALPHA 21164 |
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10
Microarchitecture
Serial Read-Only Memory Interface
A 7-bit address space number (ASN) field as defined by the Alpha architecture
A 1-bit address space match (ASM) field as defined by the Alpha architecture
A 1-bit PALcode (physically addressed) indicator
Software, rather than Icache hardware, maintains Icache coherence with memory.
3.6.3 Second-Level Cache
The second-level cache (Scache) is a 96KB, 3-way, set-associative, physical, write-
back, write-allocate cache with 32-byte or 64-byte blocks. It is a mixed data and
instruction cache. The Scache is fully pipelined; it processes read and write opera-
tions at the rate of one INT16 per CPU cycle and can alternate between read and
write accesses without bubble cycles.
When operating in 32-byte block mode, the Scache has 64-byte blocks with 32-byte
subblocks, one tag per block. If configured to 32 bytes, the Scache is organized as
three sets of 512 blocks, with each block divided into two 32-byte subblocks. If con-
figured to 64 bytes, the Scache is three sets of 512 64-byte blocks.
3.6.4 External Cache
The CBU implements control for an optional, external, direct-mapped, physical,
write-back, write-allocate cache with 32-byte or 64-byte blocks. The 21164 supports
board-level cache sizes of 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, and 64MB.
3.7 Serial Read-Only Memory Interface
The serial read-only memory (SROM) interface provides the initialization data load
path from a system SROM to the instruction cache. Following initialization, this
interface can function as a diagnostic port by using privileged architecture library
code (PALcode).
3.8 Pipeline Organization
The 21164 has a 7-stage (or 7-cycle) pipeline for integer operate and memory refer-
ence instructions, and a 9-stage pipeline for floating-point operate instructions. The
IDU maintains state for all pipeline stages to track outstanding register write opera-
tions.
Figure 2 shows the integer operate, memory reference, and floating-point operate
pipelines for the IDU, FPU, IEU, and MTU. The first four stages are executed in the
IDU. Remaining stages are executed by the IEU, FPU, MTU, and CBU.
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