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參數(shù)資料
| 型號(hào)： | Alpha 21164 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Alpha Microprocessor(64位微處理器) |
| 中文描述： | 阿爾法微處理器（64位微處理器） |
| 文件頁(yè)數(shù)： | 53/115頁(yè) |
| 文件大?。?/td> | 846K |
| 代理商： | ALPHA 21164 |
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IEEE Floating-Point Conformance
53
Underflow (UNF)
The underflow trap can be disabled. If underflow occurs, then the destination
register is forced to a true zero, consisting of a full 64 bits of zero. This is done
even if the proper IEEE result would have been -0. The exception is signaled if
the rounded result is smaller in magnitude than the smallest finite number that
can be represented by the destination format. If the exception occurs, then
FPCR<UNF> is set. If the trap is enabled, then the trap is signaled to the IDU.
The 21164 never produces a denormal number; underflow occurs instead.
Inexact (INE)
The inexact trap can be disabled. The destination register always contains the
properly rounded result, whether the trap is enabled. The exception is signaled if
the rounded result is different from what would have been produced if infinite
precision (infinitely wide data) were available. For floating-point results, this
requires both an infinite precision exponent and fraction. For integer results, this
requires an infinite precision integer and an integral result. If the exception
occurs, then FPCR<INE> is set. If the trap is enabled, then the trap is signaled to
the IDU.
The IEEE-754 specification allows INE to occur concurrently with either OVF
or UNF. Whenever OVF is signaled (if the inexact trap is enabled), INE is also
signaled. Whenever UNF is signaled (if the inexact trap is enabled), INE is also
signaled. The inexact trap also occurs concurrently with integer overflow. All
valid opcodes that enable INE also enable both overflow and underflow.
If a CVTQL results in an integer overflow (IOV), then FPCR<INE> is automati-
cally set. (The INE trap is never signaled to the IDU because there is no CVTQL
opcode that enables the inexact trap.)
Integer overflow (IOV)
The integer overflow trap can be disabled. The destination register always con-
tains the low-order bits (<64> or <32>) of the true result (not the truncated bits).
Integer overflow can occur with CVTTQ, CVTGQ, or CVTQL. In conversions
from floating to quadword integer or longword integer, an integer overflow
occurs if the rounded result is outside the range
2
63
..2
63
1
. In conversions from
quadword integer to longword integer, an integer overflow occurs if the result is
outside the range
2
31
..2
31
1
. If the exception occurs, then the appropriate bit in
the FPCR is set. If the trap is enabled, then the trap is signaled to the IDU.
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