參數(shù)資料
型號(hào)： Alpha 21164
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Alpha Microprocessor(64位微處理器)
中文描述： 阿爾法微處理器（64位微處理器）
文件頁數(shù)： 48/115頁
文件大?。?/td> 846K
代理商： ALPHA 21164
48
21164 Microprocessor Functional Overview
Test Modes
srom_oe_l
srom_clk_h
During system reset, the 21164 samples the
srom_present_l
signal for the presence
of SROM. If no SROMs are detected at reset, then
srom_present_l
is deasserted and
the SROM load is disabled. The reset sequence clears the Icache valid bits, which
causes the first instruction fetch to miss the Icache and seek instructions from offchip
memory.
If SROMs are present during setup, then the system performs an SROM load as fol-
lows:
1.
The
srom_oe_l
signal supplies the output enable to the SROM.
2.
The
srom_clk_h
signal supplies the clock to the ROM that causes it to advance
to the next bit. The cycle time of this clock is 126± times the system clock ratio.
The
srom_data_h
signal reads the SROM data.
3.
5.5.3 Serial Terminal Port
After the serial ROM data is loaded into the Icache, the three SROM load signals
become parallel I/O pins that can drive a diagnostic terminal such as an RS422.
5.5.4 IEEE 1149.1 Test Access Port
The test access port complies with all requirements of the IEEE 1149.1 (JTAG) stan-
dard. The following signals make up the test access port:
tms_h
—Test access port select.
trst_l
—Test access port reset.
tck_h
—Test access port clock.
tdi_h
and
tdo_h
—Input and output for serial boundary-scan, die-ID, bypass, and
instruction registers.
5.5.5 Test Status Signals
The
test_status_h
signals extract test status information from the chip.
The
test_status_h<0>
signal indicates when the Icache built-in self-test (BiSt)
fails.
The
test_status_h<1>
signal detects unrepairable Icache by indicating more
than two failing Icache rows.
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