參數(shù)資料
型號(hào): Alpha 21164
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Alpha Microprocessor(64位微處理器)
中文描述: 阿爾法微處理器(64位微處理器)
文件頁數(shù): 87/115頁
文件大?。?/td> 846K
代理商: ALPHA 21164
Electrical Data
87
AC Characteristics
11.4.2 Pin Timing
The following sections describe Bcache loop timing, sys_clk-based system timing,
and reference clock-based system timing.
11.4.2.1 Backup Cache Loop Timing
The 21164 can be configured to support an optional offchip backup cache (Bcache).
Private Bcache read or write (Scache victims) transactions initiated by the 21164 are
independent of the system clocking scheme. Bcache loop timing must be an integer
multiple of the 21164 cycle time.
Table 27 lists the Bcache loop timing.
Outgoing Bcache index and data signals are driven off the internal clock edge and
the incoming Bcache tag and data signals are latched on the same internal clock
edge. Table 28 and Table 29 show the output driver characteristics for the normal
driver and big driver respectively.
1
The value 0.4 ns accounts for onchip driver and clock skew.
2
The value 0.2 ns accounts for onchip driver and clock skew.
3
See 21164 change document for the positioning of
st_clk1_h
and
st_clk2_h
with respect to the Bcache index
pins.
4
For big drive enabled or big drive disabled, respectively. See Table 29.
Table 27 Bcache Loop Timing
Value
Signal
Specification
366 MHz – 500 MHz
Faster than 500 MHz
Name
data_h<127:0>
Input setup
1.2 ns
1.1 ns
Tdsu
data_h<127:0>
Input hold
0.0 ns
Tdd
+
Tcycle
+ 0.4 ns
1
0.1 ns
Tdd
+
Tcycle
+ 0.2 ns
2
Tdh
data_h<127:0>
Output delay
Tdod
data_h<127:0>
Output hold
Tmdd
+
Tcycle
Tmdd
+
Tcycle
Tdoh
index_h<25:4>
,
st_clk1_h
,
st_clk2_h
3
Output delay
Tbedd
+ 0.4 ns,
or
Tbddd
+ 0.4 ns
1,4
Tbedd
+ 0.2 ns,
or
Tbddd
+ 0.2 ns
2,4
Tiod
index_h<25:4>,
st_clk1_h, st_clk2_h
3
Output hold time
Tmdd
Tmdd
Tioh
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