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參數(shù)資料
| 型號： | ADMC401BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 38/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 8CH 12BIT MOTCTRL 144LQFP |
| 標準包裝： | 1 |
| 系列： | 電機控制 |
| 類型： | 定點 |
| 接口： | 串行端口 |
| 時鐘速率： | 26MHz |
| 非易失內(nèi)存： | ROM（6 kB） |
| 芯片上RAM： | 8kB |
| 電壓 - 輸入/輸出： | 5.00V |
| 電壓 - 核心： | 5.00V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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ADMC401
–43–
REV. B
Interrupt Configuration
The IFC and ICNTL registers of the DSP core control and
configure the interrupt controller of the DSP core. The IFC
register is a 16-bit register that may be used to force and/or clear
any of the eight DSP interrupts. Bits 0 to 7 of the IFC register
may be used to clear the DSP interrupts while Bits 8 to 15 can be
used to force a corresponding interrupt. Writing to Bits 11 and 12
in IFC is the only way to create the two software interrupts.
The ICNTL register is used to configure the sensitivity (edge or
level) of the
IRQ0, IRQ1 and IRQ2 interrupts and to enable/
disable interrupt nesting. Setting Bit 0 of ICNTL configures the
IRQ0 as edge sensitive while clearing the bit configures it for
level sensitive. Bit 1 is used to configure the
IRQ1 interrupt and
Bit 2 is used to configure the
IRQ2 interrupt. It is recommended
that the
IRQ2 interrupt be always configured for level sensitive
as this ensures that no peripheral interrupts are lost. Setting Bit 4
of the ICNTL register enables interrupt nesting. The configura-
tion of both IFC and ICNTL registers is shown at the end of
the data sheet.
Interrupt Operation
Following a reset (with ROMENABLE = 1), the ROM code
monitor of the ADMC401 copies a default interrupt vector table
into program memory RAM from address 0x0000 to 0x005F.
Since each interrupt source has a dedicated four word space in
this vector table, it is possible to code short interrupt service
routines (ISR) in place. Alternatively, it may be required to
insert a JUMP instruction to the appropriate start address of the
interrupt service routine if more memory is required for the ISR.
On the occurrence of an interrupt, the program sequencer en-
sures that there is no latency (beyond synchronization delay)
when processing unmasked interrupts. In the case of the timer,
SPORT0, SPORT1 and software interrupts, the interrupt con-
troller automatically jumps to the appropriate location in the
interrupt vector table. At this point, a JUMP instruction to the
appropriate ISR is required.
In the event of a motor control peripheral interrupt, the opera-
tion is slightly different. For any of the eleven peripheral inter-
rupts, the interrupt controller automatically jumps to location
0x0004 in the interrupt vector table. In addition, the required
vector address (between 0x0030 and 0x0058) associated with
the particular interrupt source is placed in the PICVECTOR
register of the PIC block. Code loaded at location 0x0004 by
the monitor on reset subsequently performs a JUMP from loca-
tion 0x0004 to the address specified in the PICVECTOR regis-
ter. This operation with the PICVECTOR register results in a
slightly longer latency associated with processing any of the
peripheral interrupts, as compared with the latency of the inter-
nal DSP core interrupts.
The code located at location 0x0004 by the monitor on reset is
as follows:
0x0004: DM (I4_SAVE) = I4;
I4 = DM (PICVECTOR);
JUMP (I4
);
The default code for each of the motor control peripherals is:
I4 = DM (I4_SAVE);
RTI;
Note that this default restores I4 to its value before the inter-
rupt. The user should replace the RTI with a JUMP to their
ISR. The PUT_VECTOR ROM subroutine can be used to
replace the RTI with the JUMP.
The PIC block manages the sequencing of the eleven motor
control peripheral interrupts. In the case of multiple simulta-
neous interrupts, the PIC will load the PICVECTOR register
with the vector address of the highest priority pending interrupt.
The contents of the PICVECTOR register will remain fixed
until read by the DSP. This action is performed by the default
DSP code at location 0x0004. The PIC block only asserts a
new interrupt after the PICVECTOR register has been read.
For other settings of MMAP and BMODE the user must cor-
rectly configure the vector table.
SYSTEM CONTROLLER
MODECTRL REGISTER
The MODECTRL register controls three important features of
the ADMC401. It internally configures the SPORT1 pins for
boot loading and UART debugging. Dedicated bits in the
MODECTRL register also control the operating mode of the
PWM generation unit (single or double update mode) and the
operating mode of the auxiliary PWM generation unit (indepen-
dent or offset mode).
Two bits of the MODECTRL register control the internal con-
figuration of the SPORT1 pins as illustrated in Figure 34. Bit 4
(DR1SEL) selects which of the two external receive pins (DR1A
or DR1B) is connected to the internal data receive port of the
DSP core. Clearing Bit 4 selects the DR1A pin, whereas setting
Bit 4 selects the DR1B pin. Following reset, Bit 4 is cleared so
that DR1A is selected.
DSP CORE
DR1A
DR1B
TFS1
RFS1/
SROM
MODECTRL (5…4)
UARTEN
DR1SEL
DT1
DR1
TFS1
RFS1
FL1
ADMC401
DT1
SCLK1
Figure 34. Internal Multiplexing of SPORT1 Pins
Bit 5 (UARTEN) of the MODECTRL register is used to select
between UART and SPORT mode of SPORT1. Setting the
UARTEN bit connects DR1A to the RFS1 input which allows
SPORT1 to be used as a UART port. Additionally, the internal
FL1 flag of the DSP core is connected to the RFS1/
SROM pin
of the ADMC401, to be used as a reset for the external serial
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