參數(shù)資料
型號(hào)： ADMC401BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/60頁(yè)
文件大?。?/td> 0K
描述： IC DSP 8CH 12BIT MOTCTRL 144LQFP
標(biāo)準(zhǔn)包裝： 1
系列： 電機(jī)控制
類型： 定點(diǎn)
接口： 串行端口
時(shí)鐘速率： 26MHz
非易失內(nèi)存： ROM（6 kB）
芯片上RAM： 8kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
REV. B
ADMC401
–18–
When MMAP = 1 and BMODE = 0, the internal program
memory RAM is mapped to the top of the program memory space
(starting at address 0x3800) and no boot loading occurs. Program
execution starts from external program memory at address 0x0000.
Only with ROMENABLE = 1 are the internal ROM monitor
and debugger features of the ADMC401 available for program
development. Additionally, certain spaces of the memory map
have predefined functions as illustrated in Figure 12 where it
can be seen that address space 0x0000 to 0x005F is reserved for
the interrupt vector table.
VECTOR TABLE
USER
PROGRAM
SPACE
0x000
ROM
MONITOR
RESERVED
EXTERNAL
MEMORY
0x05F
0x060
0x7FF
0x800
0xFEF
0xFF0
0xFFF
0x1000
Figure 12. Detailed View of Program Memory Map with
MMAP = BMODE = 1
The program memory interface can generate 0 to 7 wait states
for external memory devices. The program memory wait state
field (PWAIT) in the System Control Register controls the number
of inserted wait states and defaults to 7. The structure of the
System Control Register is shown at the end of the data sheet.
The data memory map of the ADMC401 is shown in Figure 13.
The internal data memory RAM of the ADMC401 is arranged
as a single 1K
× 16-bit block starting at address 0x3800. In
addition, there are two 1K blocks of reserved data memory
space; one block starting at address 0x2000 that is reserved for
the peripheral registers and one starting at address 0x3C00 that
is reserved for internal DSP core registers. Data memory wait
states are controlled by the DWAIT0, DWAIT1, DWAIT2,
DWAIT3 and DWAIT4 fields of the Data Memory Wait State
Register (MEMWAIT) as illustrated in Figure 13. Following
reset, DWAIT0 = DWAIT1 = DWAIT2 = DWAIT 3 =
DWAIT4 = 7. However, in standalone mode with MMAP =
BMODE = 1, the internal monitor code writes 0 to these five
fields. For correct operation DWAIT2 must always be 0. The
configuration of the MEMWAIT register is shown at the end of
the data sheet.
0x0000
8K EXTERNAL
MEMORY
0x23FF
0x2400
0x1FFF
0x2000
PERIPHERAL
REGISTERS
5K EXTERNAL
MEMORY
DSP CORE
REGISTERS/
RESERVED
INTERNAL USER
RAM
0x37FF
0x3800
0x3BFF
0x3C00
0x3FFF
0x3B5F
0x3B60
RESERVED BY
MONITOR
0x0000
0x03FF
0x0400
DWAIT0
0x2FFF
0x3000
0x3FFF
DWAIT1
DWAIT2
NO WAIT
STATES
0x07FF
0x0800
DWAIT3
DWAIT4
0x3400
0x3800
Figure 13. Data Memory Map of the ADMC401
ROM Code
The 2K
× 24-bit block of internal program memory ROM start-
ing at address 0x800 contains a monitor function that can be
used to download and execute user programs via the serial port.
In addition, the monitor function supports an interactive mode
in which commands are received and processed from a host that
is configured as a UART device. An example of such a host is
the Windows-based Motion Control Debugger that is part of
the software development system for the ADMC401. In the
interactive mode, the host can access both the internal DSP and
peripheral motor control registers of the ADMC401, read and
write to both program and data memory, implement break-
points and perform single-step operation as part of the program
debugging cycle. Again, this debugging feature is only available
when ROMENABLE = 1.
2K INTERNAL RAM
(BOOTED FROM
BYTE-WIDE EPROM)
2K INTERNAL ROM
(ROMENABLE = 1)
OR
2K EXTERNAL
(ROMENABLE = 0)
12K EXTERNAL
MEMORY
0x0000
0x0FFF
0x1000
0x07FF
0x0800
0x3FFF
MMAP = 0
BMODE = 0
2K EXTERNAL
MEMORY
10K EXTERNAL
MEMORY
0x0000
0x0FFF
0x1000
0x07FF
0x0800
0x3FFF
MMAP = 1
BMODE = 0
2K INTERNAL RAM
(BOOTED VIA
SPORT1)
2K INTERNAL ROM
(ROMENABLE
DEFAULTS TO 1
DURING RESET)
0x0000
0x0FFF
0x1000
0x07FF
0x0800
0x3FFF
MMAP = 1
BMODE = 1
0x3800
2K INTERNAL RAM
2K INTERNAL ROM
(ROMENABLE = 1)
OR
2K EXTERNAL
(ROMENABLE = 0)
12K EXTERNAL
MEMORY
Figure 11. Program Memory Map of ADMC401
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