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參數(shù)資料
| 型號： | ADMC401BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 8CH 12BIT MOTCTRL 144LQFP |
| 標準包裝： | 1 |
| 系列： | 電機控制 |
| 類型： | 定點 |
| 接口： | 串行端口 |
| 時鐘速率： | 26MHz |
| 非易失內(nèi)存： | ROM（6 kB） |
| 芯片上RAM： | 8kB |
| 電壓 - 輸入/輸出： | 5.00V |
| 電壓 - 核心： | 5.00V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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ADMC401
–11–
REV. B
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C
× V
DD
2
× f
C = load capacitance, f = output switching frequency.
Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:
External data memory is accessed every cycle with 50% of the
address pins switching.
External data memory writes occur every other cycle with
50% of the data pins switching.
Each address and data pin has a 10 pF total load at the pin.
The application operates at VDD = 5.0 V and tCK = 38.5 ns.
Total Power Dissipation = PINT + (C
× V
DD
2
× f)
PINT = VDD
× (I
DD Digital + IDD Analog)
(C
× V
DD
2
× f) is calculated for each output:
# of
Pins
C
VDD
2
f
Address,
DMS
8
× 10 pF × 52 V
× 26 MHz
= 52.00 mW
Data Output,
WR 9
× 10 pF × 52 V
× 13 MHz
= 29.25 mW
RD
1
× 10 pF × 52 V
× 13 MHz
=
3.25 mW
CLKOUT
1
× 10 pF × 52 V
× 26 MHz
=
6.50 mW
91.00 mW
Total power dissipation for this example is PINT + 91 mW.
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (tDIS) is the difference of tMEASURED and tDECAY,
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitative load, CL, and the cur-
rent load, iL, on the output pin. It can be approximated by the
following equation:
t
CV
I
DECAY
L
=
× 05
.
from which
tt
t
DIS
MEASURED
DECAY
=
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
3.0V
1.5V
0.0V
2.0V
1.5V
0.3V
INPUT
OUTPUT
Figure 7. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when
the output has reached a specified high or low trip point, as
shown in the Output Enable/Disable diagram. If multiple pins
(such as the data bus) are enabled, the measurement value is
that of the first pin to start driving.
2.0V
1.0V
tENA
REFERENCE
SIGNAL
OUTPUT
tDECAY
VOH
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
tDIS
tMEASURED
VOL
(MEASURED)
VOH (MEASURED) – 0.5V
VOL (MEASURED) +0.5V
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
VOH
(MEASURED)
VOL
(MEASURED)
Figure 8. Output Enable/Disable
TO
OUTPUT
PIN
50pF
+1.5V
IOH
IOL
Figure 9. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)
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