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參數(shù)資料
| 型號： | ADMC401BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/60頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 8CH 12BIT MOTCTRL 144LQFP |
| 標準包裝： | 1 |
| 系列： | 電機控制 |
| 類型： | 定點 |
| 接口： | 串行端口 |
| 時鐘速率： | 26MHz |
| 非易失內存： | ROM（6 kB） |
| 芯片上RAM： | 8kB |
| 電壓 - 輸入/輸出： | 5.00V |
| 電壓 - 核心： | 5.00V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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ADMC401
–35–
REV. B
register is set and an EIU count error interrupt is generated.
An additional status bit is provided in the EIUSTAT register
that indicates the initialization state of the EIU. Until the
EIUMAXCNT register is written to, the EIU is not initialized.
Four status bits in the EIUSTAT register provide the state of the
four EIU inputs, EIA, EIB, EIZ and EIS.
The encoder interface unit of the ADMC401 contains a 16-bit
loop timer that behaves in a manner similar to the program-
mable interval timer of the DSP core. The loop timer consist of
a timer register, period register and scale register so that it can
be programmed to timeout and reload at appropriate intervals.
A control bit in the EIUCTRL register is used to enable/disable
this loop timer. When this loop timer times out, an EIU loop
timer timeout interrupt is generated. This interrupt could be
used to control the timing of speed and position control loops in
high performance drives.
The encoder interface unit also includes a high performance
encoder event timer (EET) block that permits the accurate
timing of successive events of the encoder inputs. The EET can
be programmed to time the duration between up to 255 encoder
pulses and can be used to enhance velocity estimation, particu-
larly at low speeds of rotation. The information from the regis-
ters of the EET block can be latched in two ways. In one mode,
the contents of the EIU quadrature count register, EIUCNT
and all relevant EET registers (EETT and EETDELTAT) are
latched when the EIU loop timer times out. In the second mode,
the act of reading the EIUCNT register also simultaneously
latches the EET registers. The EET data latching mode is se-
lected by a control bit in the EIUCTRL register.
ENCODER LOOP TIMER
The EIU contains a 16-bit loop timer that is structured in a
manner similar to the interval timer of the DSP core (TCOUNT,
TPERIOD and TSCALE registers). The corresponding regis-
ters of the encoder loop timer are the 16-bit EIUTIMER and
EIUPERIOD registers and the 8-bit EIUSCALE register. The
EIU loop timer is clocked at the CLKOUT rate, tCK.
The EIU loop timer can be used to generate periodic interrupts
based on multiples of the DSP cycle time. The EIU loop timer
is enabled by setting Bit 5 of the EIUCTRL register. When
enabled, the 16-bit timer register (EIUTIMER) is decremented
every N cycles, where N-1 is the scaling value stored in the 8-bit
EIUSCALE register. When the value of the EIUTIMER register
reaches zero, the EIU loop timer timeout interrupt is generated
and the EIUTIMER register is reloaded with the 16-bit value in
the EIUPERIOD register. The scaling feature of this timer,
provided by the EIUSCALE register, allows the 16-bit timer to
generate periodic interrupts over a wide range of periods. For a
26 MHz CLKOUT rate (38.5 ns period), the timer can gener-
ate interrupts with periods of 38.5 ns up to 2.52 ms with a zero
scale value (EIUSCALE = 0). When scaling is used, time peri-
ods can range up to 0.645 sec. The EIU loop timer timeout
interrupt can be masked in the PICMASK register.
ENCODER INTERFACE STRUCTURE AND OPERATION
Introduction
The encoder interface section consists of a 16-bit quadrature
up/down counter and a 16-bit EIUCNT register that allows the
up/down counter to be read by the DSP. There is also a 16-bit
EIUMAXCNT register that must be written to, to initialize the
encoder system. Until the EIUMAXCNT register has been
written to, the encoder interface unit is not initialized and
Bit 2 of the EIUSTAT register is set. The contents of the
EIUMAXCNT register are used in certain operating modes to
reset the quadrature counter. The contents of the EIUMAXCNT
register are also used for error checking of the EIU. Operation
of the encoder interface is controlled by the EIUCTRL register.
Programmable Input Noise Filtering of Encoder Signals
A functional block diagram of the input stages of the encoder
interface is shown in Figure 29. The four encoder input signals
(EIA, EIB, EIZ and EIS) are first synchronized in input syn-
chronization buffers. This eliminates the asynchronous nature of
real world encoder signals prior to use in the encoder interface
unit logic. Subsequently, all four synchronized signals (EIAS,
EIBS, EIZS and EISS) are applied to programmable noise filter-
ing circuits that can be programmed to reject pulses that are
shorter than some suitable value. The outputs of the filter stage
are applied to the quadrature counter stage.
EIA
EIB
EIZ
EIS
CLKOUT
CLOCK
DIVIDE
EIUFILTER(5…0)
EIAS
EIBS
EIZS
EISS
A
B
Z
S
THREE STAGE
DIGITAL FILTER
INPUT
SYNCHRONIZA-
TION
STAGE
Figure 29. Functional Block Diagram of Input Stage
of Encoder Interface
Each of the four synchronized input signals (EIAS, EIBS, EIZS
and EISS) is applied to a three clock cycle delay filter such that
the filtered output signals are not permitted to change until a
stable value has been registered for three successive clock cycles.
While the encoder signals are changing, the filter maintains the
previous output value. The clock frequency used for the filter
circuits is programmed by Bits 0 to 5 of the EIUFILTER regis-
ter. The 6-bit quantity written to Bits 0 to 5 of the EIUFILTER
register is used to divide the CLKOUT frequency and provide
the clock source for the encoder noise filters. If the value written
to Bits 0 to 5 of the EIUFILTER register is N, the period of the
clock source used in the encoder filters is (N + 1)
× tCK. This
filter structure guarantees that encoder pulses of less width than
2
× (N + 1) × t
CK will always be rejected by the filter stage.
Additionally, pulses greater than 3
× (N + 1) × tCK will always
get through the filter stage and be passed to the internal quadra-
ture counter. Encoder pulses of widths between 2
× (N + 1) ×
tCK and 3
× (N+1) × tCK may either pass through or be rejected
by the encoder filter. Whether or not such pulses pass through
the filter depends on the exact nature of the synchronization
between the external asynchronous pulses and the internal DSP
clock and is impossible to predict.
For example, writing a value of 3 to the EIUFILTER register,
means that the clock frequency used in the encoder filters is
6.5 MHz (for a CLKOUT rate of 26 MHz). In order to register
as a stable value, the encoder input signals must be stable for
three of these 6.5 MHz cycles (or 462 ns). Consequently, the
smallest period that will be registered on the synchronized en-
coder inputs is 924 ns, corresponding to a maximum encoder
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