參數(shù)資料
型號(hào)： ADMC401BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/60頁(yè)
文件大小： 0K
描述： IC DSP 8CH 12BIT MOTCTRL 144LQFP
標(biāo)準(zhǔn)包裝： 1
系列： 電機(jī)控制
類型： 定點(diǎn)
接口： 串行端口
時(shí)鐘速率： 26MHz
非易失內(nèi)存： ROM（6 kB）
芯片上RAM： 8kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
ADMC401
–25–
REV. B
Simultaneous Sampling Mode
This operating mode is selected by clearing both Bits 3 and 4 of
the ADCCTRL register. In this mode, the eight analog inputs
are sampled as four pairs of simultaneously sampled inputs with
VIN0 and VIN4 being the first pair of sampled inputs, followed
by VIN1 and VIN5, followed by VIN2 and VIN6, followed by
VIN3 and VIN7. Following the rising edge of the convert start
command (either internally or externally derived), the internal
control logic simultaneously samples the VIN0 and VIN4 analog
inputs using the dual internal sample and hold amplifiers. The
internal control logic subsequently multiplexes these two signals
into the A/D core of the ADMC401. The conversion of each
signal requires 3 1/2 ADC clock cycles. Following the hold
operation, the VIN0 input is applied to the first stage of the
pipeline during the next ADC clock cycle. For the next clock
cycle, the VIN0 signal is applied to the second stage of the
pipeline and the VIN4 input is applied to the first stage of this
pipeline. In this clock cycle, the second pair of inputs is also
simultaneously sampled. This process continues to feed signals
into the A/D core until all eight channels have been converted.
The timing of this conversion sequence is shown in Figure 19.
CONVERT VIN7
S&H VIN3 & VIN7
S&H VIN1 & VIN5
S&H VIN2 & VIN6
CONVERT
START
ADC
CLOCK
S&H VIN0 & VIN4
CONVERT VIN0
CONVERT VIN4
CONVERT VIN1
CONVERT VIN5
CONVERT VIN2
CONVERT VIN6
CONVERT VIN3
tCKADC
Figure 19. ADC Timing for Simultaneous Sampling Oper-
ating Mode
In this operating mode, there is a unique status bit in the
ADCSTAT register that is set as soon as data is available for
each pair of simultaneously sampled signals. Bit 0 of the
ADCSTAT is set as soon as the data in both the ADC0 and
ADC4 registers is valid, Bit 1 is set as soon as the data in ADC1
and ADC5 is valid, Bit 2 is set as soon as the data in ADC2 and
Table II. Digital Data Format of ADC
VIN0 (V)
ASHAN (V)
VCORE (V)
Digital Data (Hex)
Digital Data (Binary)
OTR
≥2 × V
REF
VREF
≥+V
REF
0x7FF0
0111 1111 1111 0000
1
2
× VREF – 1 LSB
VREF
VREF – 1 LSB
0x7FF0
0111 1111 1111 0000
0
2
× VREF – 2 LSB
VREF
VREF – 2 LSB
0x7FE0
0111 1111 1110 0000
0
VREF + 1 LSB
VREF
0 + 1 LSB
0x0010
0000 0000 0001 0000
0
VREF
0
0x0000
0000 0000 0000 0000
0
VREF – 1 LSB
VREF
0 – 1 LSB
0xFFF0
1111 1111 1111 0000
0
0 + 1 LSB
VREF
–VREF + 1 LSB
0x8010
1000 0000 0001 0000
0
0VREF
–VREF
0x8000
1000 0000 0000 0000
0
< 0
VREF
<–VREF
0x8000
1000 0000 0000 0000
1
where AVSS is nominally at 0 V and AVDD is nominally at +5 V. Of
course, identical input constraints and requirements apply for
the other analog inputs VIN1 to VIN7 as well as the BSHAN
and GAIN inputs.
ADC DATA FORMAT AND OUT-OF-RANGE DETECTION
The digital data from the A/D core that is stored in the dedi-
cated, memory mapped ADC registers (ADC0 to ADC7 as well
as ADCXTRA) is stored as left-aligned, twos complement data.
The output data format for normal operation in the single-
ended configuration of Figure 18 is given in Table II for one
analog input (VIN0 and ASHAN). Naturally, identical condi-
tions apply for all other analog inputs.
As well as the 12-bit data word, the A/D core produces an out-
of-range bit that is set when the analog input to the core exceeds
the allowable range (–VREF to +VREF). There is a dedicated 8-bit
ADCOTR register that stores the eight OTR bits for the A/D
conversions of the signals on the VIN0 to VIN7 inputs. There is
a single bit for each analog input; if Bit 0 of the ADCOTR register
is set, the VIN0 input has exceeded the permissible input range.
Therefore, following a complete conversion cycle, if this register
is zero, no signal has exceeded the input range. If the OTR bit
for a given analog input is set, it is possible to determine if the
signal has overranged (less than 2
× V
REF) or underranged (less
than 0 V) by monitoring the MSB of the data word and the
OTR bit, as outlined in Table III.
Table III. Out-of-Range Truth Table
OTR
MSB
Condition
0
In Range: VREF
≤ VIN0 ≤ 2 × V
REF –1 LSB
0
1
In Range: 0
≤ VIN0 ≤ VREF – 1 LSB
1
0
Overrange: VIN0
≥ 2 × VREF
1
Underrange: VIN0 < 0
ADC OPERATING MODES
The A/D conversion system of the ADMC401 may be config-
ured to operate in four basic modes that are selected by Bits 3
and 4 of the ADCCTRL register. Following reset, the default
setting is that both of these bits are cleared and Simultaneous
Sampling mode is selected.
Simultaneous Sampling Mode (ADCCTRL(4 . . . 3) = 00)
Sequential Sampling Mode (ADCCTRL(4 . . . 3) = 01)
Offset Calibration Mode (ADCCTRL(4 . . . 3) = 10)
Gain Calibration Mode (ADCCTRL(4 . . . 3) = 11)
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