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參數(shù)資料
| 型號： | ADMC401BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/60頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 8CH 12BIT MOTCTRL 144LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 電機(jī)控制 |
| 類型： | 定點(diǎn) |
| 接口： | 串行端口 |
| 時(shí)鐘速率： | 26MHz |
| 非易失內(nèi)存： | ROM（6 kB） |
| 芯片上RAM： | 8kB |
| 電壓 - 輸入/輸出： | 5.00V |
| 電壓 - 核心： | 5.00V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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ADMC401
–37–
REV. B
moving in the reverse direction, the zero marker is recognized at
the falling edge of the signal at the EIZ pin.
When the ZERO bit of the EIUCTRL register is cleared, the
zero marker is not used to reset the counter. In this mode, the
contents of the EIUMAXCNT register are used as the reset
value for the up/down counter. For example, for an N-line
incremental encoder, the appropriate value to write to the
EIUMAXCNT register is 4N–1. Therefore, for a 1024 line
encoder, a value of 0x0FFF (= 4095) would be written to the
EIUMAXCNT register. However, since absolute position infor-
mation is not available in this mode, due to the absence of the
zero marker, the full 16-bit range of the quadrature counter may
be employed by writing a value of 0xFFFF to the EIUMAXCNT
register. Following a reset, the ZERO bit is cleared. The value
written to the EIUMAXCNT register must be in the form
4N–1, where N is any integer.
Registration Inputs and Software Zero Marker
The encoder interface unit of the ADMC401 provides two
marker signals, EIZ and EIS that are both filtered and synchro-
nized in a manner identical to the other encoder signals to pro-
duce the Z and S signals. Z can be used as a hardware reset of
the encoder counter, as described above. However, in many
applications a hardware reset of the counter may not be desir-
able. Instead, the encoder counter can be programmed to
operate in full 16-bit roll-over mode, by clearing Bit 1 of the
EIUCTRL register and programming EIUMAXCNT to be
0xFFFF. In this case, the quadrature counter will use the full
16-bit range of the EIUCNT register.
The signals on Z and S can be configured to latch the contents
of the EIUCNT register into dedicated memory mapped regis-
ters (EIZLATCH for the Z signal and EISLATCH for the S
signal) on the occurrence of definite events on these pins. The
exact nature of the events are determined by Bit 7 of the
EIUCTRL register for the Z input and Bit 8 of the EIUCTRL
register for the S signal.
If Bit 7 of the EIUCTRL register is cleared, the contents of the
EIUCNT register are latched to the EIZLATCH register on the
occurrence of a rising edge on the Z signal. In this mode, the
signals can be used to latch or freeze the EIUCNT contents on
the occurrence of an external event such as that from limit switches
or other triggers. If Bit 7 of the EIUCTRL register is set, then
the EIUCNT contents are latched to the EIZLATCH register
on the occurrence of the next quadrature pulse following the
rising edge of the Z signal if the quadrature counter is incre-
menting (count up). If the quadrature counter is decrementing,
the EIUCNT contents are latched to the EIZLATCH register
on the next quadrature pulse following the falling edge of the Z
signal. In this mode, the action resembles that of a zero marker
function. The advantage is that the EIUCNT register contents
are latched at the appropriate zero marker inputs, but the con-
tents of the quadrature counter are not affected.
Bit 8 of the EIUCTRL register defines the S events that cause
the EIUCNT register to be latched to the EISLATCH register.
When Bit 8 of the EIUCTRL register is cleared, the contents of
the EIUCNT register are latched to the EISLATCH register on
the occurrence of a rising edge on the S signal, in a manner
identical to that for the Z input. If Bit 8 of the EIUCTRL
register is set, the operation is slightly different to that for the Z
input. With the S input, the EIUCNT contents are latched to
the EISLATCH register on the occurrence of a rising edge of
the S signal if the quadrature counter is incrementing (count
up). If the quadrature counter is decrementing, the EIUCNT
contents are latched to the EISLATCH register on the occur-
rence of the falling edge of the S signal. The difference is that
the latching occurs at the event on the S input and not at the
next quadrature event (as with this case on the Z input).
EIZLATCH and EISLATCH are 16-bit read-only registers
whose state is undefined on power-up. On power-up or follow-
ing a reset, both Bits 7 and 8 of the EIUCTRL register are
cleared.
Single North Marker Mode
A further reset mode, called Single North Marker Mode, is avail-
able in the encoder interface unit . This mode is enabled by
setting Bit 2 (SNM) of the EIUCTRL register. For this mode to
operate the ZERO bit (Bit1) of the EIUCTRL register must
also be set. In this mode, the EIUCNT register is reset (to zero
or EIUMAXCNT, depending on direction) only on the first
occurrence of the zero marker. Subsequently, the EIUCNT
register is reset by the natural roll-over to zero or the value in
the EIUMAXCNT register. Following a reset, this SNM bit is
cleared. Bit 7 of the EIUSTAT register is used to signal the first
occurrence of a zero marker. When the first zero marker has been
recognized by the EIU, Bit 7 of the EIUSTAT register is set.
Encoder Error Checking
Error checking in the EIU is enabled by setting Bit 3 (MON) of
the EIUCTRL register. To be enabled, the ZERO bit of the
EIUCTRL register must also be set for error checking. In this
mode, the contents of the EIUCNT register are compared with
the expected value (zero or EIUMAXCNT depending on direc-
tion) when the zero marker is detected. If a value other than the
expected value is detected, an error condition is generated by
setting Bit 0 of the EIUSTAT register and triggering an EIU
count error interrupt. This EIU count error interrupt is man-
aged and may be masked by the programmable interrupt con-
troller (PIC) block. The encoder continues to count encoder
edges after an error has been detected. Bit 0 of the EIUSTAT
register is cleared on the occurrence of the next zero marker
provided the error condition no longer exists and the EIUCNT
register again matches the expected value. Following a reset, the
MON bit is cleared.
Encoder Input Status
Four additional status bits are provided in the EIUSTAT regis-
ter that provide a measure of the state of the four EIU inputs
following the synchronization buffers and input filter. Bit 3 indi-
cates the state of the EIA signal, Bit 4 indicates the state of the
EIB signal, Bit 5 gives the state of the EIZ signal and Bit 6 gives
the state of the EIS signal. The value of these status bits read is
not affected by any of the control bits in the EIUCTRL register.
ENCODER EVENT TIMER
Introduction and Overview
The encoder event timer block forms an integral part of the EIU
of the ADMC401, as shown in Figure 28. The EET accurately
times the duration between encoder events. The information
provided by the EET may be used to make allowances for the
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