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| 型號： | ADN4605ABPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWITCH 352BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 交叉點(diǎn)開關(guān) |
| 電路： | 1 x 40:40 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 2.25 V ~ 3.6 V |
| 電流 - 電源： | 55mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 352-BGA-EP（35x35） |
| 包裝： | 托盤 |
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4.25 Gbps 40 × 40 Digital
Crosspoint Switch
Data Sheet
FEATURES
DC to 4.25 Gbps per port NRZ data rate
Adjustable receive equalization
3 dB, 6 dB, or 12 dB boost
Compensates over 40 inches of FR4 at 4.25 Gbps
Adjustable transmit preemphasis/deemphasis
Programmable boost and output level
Compensates over 40 inches of FR4 at 4.25 Gbps
Low power
105 mW per channel at 2.5 V (400 mV p-p differential
output level swing)
40 × 40, fully differential, nonblocking array
Double rank connection programming with dual maps
Low jitter, typically <25 ps
Flexible 2.5 V to 3.3 V supply range
DC- or ac-coupled differential PECL/CML inputs
Differential CML outputs
Per-lane polarity inversion for routing ease
50 on-chip I/O termination with disable feature
Supports 8b10b, scrambled or uncoded NRZ data
Serial (IC slave or SPI) control interface
Parallel control interface
FUNCTIONAL BLOCK DIAGRAM
EQ
Rx
Tx
PRE-
EMPHASIS
40 × 40
SWITCH
MATRIX
CONNECTION
MAP 1
CONNECTION
MAP 0
PARALLEL/SERIA L CONTROL
LOGIC INTERFACE
PRE-
EMPHASIS
LEVEL
SETTINGS
OUTPUT
LEVEL
SETTINGS
ADN4605
VCC
VEE
DVCC
OP[39:0]
VTTOA,
VTTOB
ON[39:0]
IP[39:0]
VTTIA,
VTTIB
IN[39:0]
I2C/SPI
(UPDATE)
SDI/RE
SCL/SCK/
WE
RESET
SER/PAR
CS
EQUALIZATION
SETTINGS
DATA[1]
(UPDATE)
DATA[0]/
SDA/SDO
DATA[7:2]
ADDR[7:0]
09796-
001
Figure 1.
APPLICATIONS
Digital video (HDMI, DVI, DisplayPort, 3G/HD/SD-SDI)
Fiber optic network switching
High speed serial backplane routing to OC-48 with FEC
XAUI, 4x Fibre Channel, Infiniband, and GbE over backplane
Data storage networks
GENERAL DESCRIPTION
The ADN4605 is a 40 × 40 asynchronous, protocol agnostic,
digital crosspoint switch, with 40 differential PECL/CML-
compatible inputs and 40 differential programmable CML
outputs.
The ADN4605 is optimized for NRZ signaling with data rates of
up to 4.25 Gbps per port. Each port offers adjustable levels of
input equalization, programmable output swing, and output
preemphasis/deemphasis.
The ADN4605 nonblocking switch core implements a 40 × 40
crossbar and supports independent channel switching through
serial and parallel control interfaces. The ADN4605 has low
latency and very low channel-to-channel skew.
An I2C, SPI, or parallel interface is used to communicate with
the device for control of connectivity and other features.
The ADN4605 is assembled in a 35 mm × 35 mm, 352 BGA
package and operates over a temperature range of 40°C
to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2011 Analog Devices, Inc. All rights reserved.
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