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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ADN4605ABPZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 27/56闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC CROSSPOINT SWITCH 352BGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | XStream™ |
| 鍔熻兘锛� | 浜ゅ弶榛�(di菐n)闁嬮棞(gu膩n) |
| 闆昏矾锛� | 1 x 40:40 |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | 2.25 V ~ 3.6 V |
| 闆绘祦 - 闆绘簮锛� | 55mA |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 352-LBGA 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 352-BGA-EP锛�35x35锛� |
| 鍖呰锛� | 鎵樼洡 |
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Data Sheet
ADN4605
Rev. A | Page 33 of 56
I2C SERIAL CONTROL INTERFACE
interface. To access the I2C serial interface, both the SER/PAR
line and I2C/SPI lines must be held at logic high. The ADN4605
acts only as an I2C slave device. Therefore, the I2C bus in the
system needs to include an I2C master to configure the
The ADN4605 I2C interface can be run in the standard
(100 kHz) and fast (400 kHz) modes. The SDA line only
changes value when the SCL pin is low with two exceptions.
To indicate the beginning or continuation of a transfer, the
SDA pin is driven low while the SCL pin is high; to indicate
the end of a transfer, the SDA line is driven high while the
SCL line is high. Therefore, it is important to control the
SCL clock to toggle only when the SDA line is stable unless
indicating a start, repeated start, or stop condition. To establish
(ADDR[7:1]) need to be configured to the user-assigned I2C
device address as shown in Table 17.
Table 17. Example of I2C Device Address Assignment
A7
A6
A5
A4
A3
A2
A1
A0
I2C Device Address
1
0
1
0
X
0x90
1
0
1
0
1
X
0x92
1
0
1
0
1
0
X
0x94
1
0
1
0
1
X
0x96
I2C DATA WRITE
To write data to the ADN4605 register set, a microcontroller, or
any other I2C master, must send the appropriate control signals
to the ADN4605 slave device. The steps to be followed are listed
below; the signals are controlled by the I2C master unless other-
wise specified. A diagram of the procedure is shown in Figure 46.
1. Send a start condition (while holding the SCL line high,
pull the SDA line low).
2. Send the ADN4605 part address (seven bits) whose bits are
controlled by the input pins ADDR[7:1]. This transfer
should be MSB first.
3. Send the write indicator bit (0).
4. Wait for the ADN4605 to acknowledge the request.
5. Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
6. Wait for the ADN4605 to acknowledge the request.
7. Send the data (eight bits) to be written to the register
whose address was set in Step 5. This transfer should be
MSB first.
8. Wait for the ADN4605 to acknowledge the request.
9. Do one or more of the following:
a. Send a stop condition (while holding the SCL line high,
pull the SDA line high) and release control of the bus.
b. Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of the write procedure (see the I2C Data
Write section) to perform a write.
c. Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of this procedure to perform a read from
another address.
d. Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 8 of this procedure to perform a read from
the same address.
The ADN4605 write process is shown in Figure 46. The SCL
signal is shown along with a general write operation and a
specific example. In the example, Data 0x4B is written to
Address 0x6D of an ADN4605 part with a part address of 0x92.
The ADN4605 device address selections are more flexible than
shown. It is important to note that the SDA line only changes
when the SCL line is low, except for the case of sending a start,
stop, or repeated start condition, Step 1 and Step 9 in this case.
START
R/W ACK
ACK
STOP
DATA
ADDR
[1:0]
b10010
REGISTER ADDR
SCL
SDA
EXAMPLE
1
2
3
4
5
6
7
8
9a
09796-
013
Figure 46. I2C Write Diagram
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| ADN4612 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:11.3 Gbps 12X12 Digital Crosspoint |
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