參數(shù)資料
型號: ADN4664BRZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 1/12頁
文件大小: 0K
描述: IC RCVR DIFF LVDS 2CH 8SOIC
標(biāo)準(zhǔn)包裝: 1,000
類型: 線路接收器
驅(qū)動器/接收器數(shù): 0/2
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 帶卷 (TR)
Dual, 3 V, CMOS, LVDS
Differential Line Receiver
ADN4664
Rev. 0
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responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2009 Analog Devices, Inc. All rights reserved.
FEATURES
±15 kV ESD protection on output pins
400 Mbps (200 MHz) switching rates
Flow-through pinout simplifies PCB layout
100 ps channel-to-channel skew (typical)
2.5 ns maximum propagation delay
3.3 V power supply
High impedance outputs on power-down
Low power design: typically 3 mW (quiescent)
Interoperable with existing 5 V LVDS drivers
Accepts small swing (310 mV typical) differential signal
levels
Supports open, short, and terminated input fail-safe
0 V to 100 mV threshold region
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range: 40°C to +85°C
Available in surface-mount (SOIC) package
APPLICATIONS
Point-to-point data transmission
Multidrop buses
Clock distribution networks
Backplane receivers
FUNCTIONAL BLOCK DIAGRAM
ROUT1
RIN1+
RIN1–
VCC
ADN4664
GND
ROUT2
RIN2+
RIN2–
07
96
1-
0
01
Figure 1.
GENERAL DESCRIPTION
The ADN4664 is a dual, CMOS, low voltage differential
signaling (LVDS) line receiver offering data rates of over
400 Mbps (200 MHz) and ultralow power consumption.
It features a flow-through pinout for easy PCB layout and
separation of input and output signals.
The device accepts low voltage (310 mV typical) differential
input signals and converts them to a single-ended 3 V TTL/
CMOS logic level.
The ADN4664 and its companion driver, the ADN4663, offer a
new solution to high speed, point-to-point data transmission,
and a low power alternative to emitter-coupled logic (ECL) or
positive emitter-coupled logic (PECL).
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