I2C TIMING SPECIFICATIONS SDA SCL
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ADN4605ABPZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 45/56闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC CROSSPOINT SWITCH 352BGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
绯诲垪锛� XStream™
鍔熻兘锛� 浜ゅ弶榛�(di菐n)闁�(k膩i)闂�(gu膩n)
闆昏矾锛� 1 x 40:40
闆诲闆绘簮锛� 鍠浕婧�
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 2.25 V ~ 3.6 V
闆绘祦 - 闆绘簮锛� 55mA
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 352-LBGA 瑁搁湶鐒婄洡
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 352-BGA-EP锛�35x35锛�
鍖呰锛� 鎵樼洡
Data Sheet
ADN4605
Rev. A | Page 5 of 56
I2C TIMING SPECIFICATIONS
SDA
SCL
tf
tLOW
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
tf
tSU;STA
tHD;STA
tSP
tSU;STO
tr
tBUF
S
P
Sr
S
09796-
002
Figure 2. I2C Timing Diagram
Table 2. I2C Timing Specifications
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fSCL
0
500+
kHz
Hold Time for a Start Condition
tHD; STA
0.5
s
Setup Time for a Repeated Start Condition
tSU; STA
0.5
s
Low Period of the SCL Clock
tLOW
1.4
s
High Period of the SCL Clock
tHIGH
0.6
s
Data Hold Time
tHD; DAT
0.02
s
Data Setup Time
tSU; DAT
0.02
s
Rise Time for Both SDA and SCL
tr
1
300
ns
Fall Time for Both SDA and SCL
tf
1
300
ns
Setup Time for Stop Condition
tSU; STO
0.5
s
Bus Free Time Between a Stop Condition and a Start Condition
tBUF
1
ns
Bus Idle Time After a Reset
20
ns
Reset Pulse Width
20
ns
SPI TIMING SPECIFICATIONS
t1
t2
t3
t5
t6
t4
t7
t8
D7
CS
SCLK
DIN
DOUT
D6
D5
D4
D3
D2
D1
D0
X
D7
D6
D5
D4
D3
D2
D1
D0
09796-
003
Figure 3. SPI Timing Diagram
Table 3. SPI Timing Specifications
Parameter
Symbol
Min
Max
Unit
SCK Clock Frequency
fSCK
10
MHz
CS to SCLK Setup Time
t1
0
ns
SCLK High Pulse Width
t2
30
ns
SCLK Low Pulse Width
t3
30
ns
Data Access Time After SCLK Falling Edge
t4
45
ns
Data Setup Time Prior to SCLK Rising Edge
t5
10
ns
Data Hold Time After SCLK Rising Edge
t6
30
ns
CS to SCLK Hold Time
t7
0
ns
CS to SDO High Impedance
t8
45
ns
Reset Pulse Width
20
ns
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