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參數(shù)資料
| 型號： | ADN4605ABPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWITCH 352BGA |
| 標準包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 交叉點開關(guān) |
| 電路： | 1 x 40:40 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 2.25 V ~ 3.6 V |
| 電流 - 電源： | 55mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA 裸露焊盤 |
| 供應商設備封裝： | 352-BGA-EP（35x35） |
| 包裝： | 托盤 |
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ADN4605
Data Sheet
Rev. A | Page 34 of 56
I2C DATA READ
To read data from the ADN4605 register set, a microcontroller,
or any other I2C master needs to send the appropriate control
signals to the ADN4605 slave device. The steps are listed below;
the signals are controlled by the I2C master unless otherwise
specified. A diagram of the procedure is shown in Figure 47.
1. Send a start condition (while holding the SCL line high, pull
the SDA line low).
2. Send the ADN4605 part address (seven bits) whose bits are
controlled by the input pins ADDR[7:1]. This transfer
should be MSB first.
3. Send the write indicator bit (0).
4. Wait for the ADN4605 to acknowledge the request.
5. Send the register address (eight bits) from which data is
to be read. This transfer should be MSB first. The register
address is kept in memory in the ADN4605 until the part
is reset or the register address is written over with the same
procedure (Step 1 to Step 6).
6. Wait for the ADN4605 to acknowledge the request.
7. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low).
8. Send the ADN4605 part address (seven bits) whose bits are
controlled by the input pins ADDR[7:1]. This transfer
should be MSB first.
9. Send the read indicator bit (1).
10. Wait for the ADN4605 to acknowledge the request.
11. The ADN4605 then serially transfers the data (eight bits)
held in the register indicated by the address set in Step 5.
12. Acknowledge the data.
13. Do one or more of the following:
a.
Send a stop condition (while holding the SCL line high
pull the SDA line high) and release control of the bus.
b.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of the write procedure (see the I2C Data
Write section) to perform a write.
c.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of this procedure to perform a read from
another address.
d.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 8 of this procedure to perform a read from
the same address.
The ADN4605 read process is shown in Figure 47. The SCL
signal is shown along with a general read operation and a
specific example. In the example, Data 0x49 is read from
Address 0x6D of an ADN4605 part with a part address of 0x92.
The part address is seven bits wide and is composed of the
ADN4605 (ADDR[7:1]). In this example, the ADDR{1:0] bits
are set to b01.
In Figure 47, the corresponding step number is visible in the
circle under the waveform. The SCL line is driven by the I2C
master and never by the ADN4605 slave. As for the SDA line,
the data in the shaded polygons is driven by the ADN4605,
whereas the data in the nonshaded polygons is driven by the I2C
master. The end phase case shown is that of Step13a.
Note that the SDA line only changes when the SCL line is low,
except for the case of sending a start, stop, or repeated start
condition, as in Step 1, Step 7, and Step 13. In Figure 47, A is
the same as ACK. Equally, Sr represents a repeated start where
the SDA line is brought high before SCL is raised. SDA is then
dropped while SCL is still high.
SCL
SDA
EXAMPLE
1
2
3
4
5
6
7
8
9
10
11
12
13a
b10010
A
Sr
DATA
A
STOP
REGISTER ADDR
START
ADDR
[1:0]
ADDR
[1:0]
b10010
R/
W
A
R/
W
09796-
014
Figure 47. I2C Read Diagram
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