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| 型號： | ADMC401BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 8CH 12BIT MOTCTRL 144LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 電機(jī)控制 |
| 類型： | 定點(diǎn) |
| 接口： | 串行端口 |
| 時鐘速率： | 26MHz |
| 非易失內(nèi)存： | ROM（6 kB） |
| 芯片上RAM： | 8kB |
| 電壓 - 輸入/輸出： | 5.00V |
| 電壓 - 核心： | 5.00V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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ADMC401
–31–
REV. B
Full ON: The PWM for any pair of PWM signals is said to
operate in FULL ON when the desired HI side output of the
three-phase Timing Unit is in the ON state (LO) between
successive PWMSYNC pulses. This state may be entered by
virtue of the commanded duty cycle values (in conjunction
with the PWMDT register) or by virtue of the correct opera-
tion of the pulse deletion circuit.
Full OFF: The PWM for any pair of PWM signals is said to
operate in FULL OFF when the desired HI side output of
the three-phase Timing Unit is in the OFF state (HI) be-
tween successive PWMSYNC pulses. This state may be
entered by virtue of the commanded duty cycle values (in
conjunction with the PWMDT register) or by virtue of the
correct operation of the pulse deletion circuit.
Normal Modulation: The PWM for any pair of PWM
signals is said to operate in normal modulation when the
desired output duty cycle is other than 0% or 100% between
successive PWMSYNC pulses.
There are certain situations when transitioning either into or out
of either full ON or full OFF where it is necessary to insert
additional dead time delays to prevent potential shoot through
conditions in the inverter. The particular situation also depends
on whether operation is in single or double update mode. In
double update mode, it is also necessary to consider whether the
PWM unit is transitioning from the first half cycle to the second
half cycle or vice versa. These transitions are detected automati-
cally by the ADMC401 and, if appropriate, the dead time is
inserted.
The insertion of the additional dead time into one of the PWM
signals of a given pair during these transitions is only needed if
otherwise both PWM signals would be required to toggle at the
PWMSYNC boundary. The additional dead time delay is in-
serted into the PWM signal that is toggling into the ON state.
In effect the turn ON of this signal is delayed by an amount
2
× PWMDT × t
CK from the rising edge of PWMSYNC. After
this delay, the PWM signal is allowed to turn ON, provided the
desired output is still the ON state after the dead time delay.
Figure 24 illustrates two examples of such transitions where in
Figure 24(a) when transitioning from normal modulation to full
ON at the half cycle boundary in double update mode, no special
action is needed. However, in Figure 24(b) when transitioning into
full OFF at the same boundary, it can be seen that an additional
dead time is necessary.
2
PWMDT
PWMCHA1
FULL ON
AH
AL
2
PWMDT
FULL OFF
AH
AL
(a)
(b)
PWMTM
DEAD TIME INSERTED
Figure 24. Examples of transitioning form normal modu-
lation into either Full ON or Full OFF where it may be nec-
essary to insert additional dead times.
Minimum Pulsewidth, PWMPD Register
In many power converter switching applications, it is desirable
to eliminate PWM switching signals below a certain width. It
takes a certain finite time to both turn on and turn off power
semiconductor devices. Therefore, if the width of any of the
PWM signals goes below some minimum value, it may be desir-
able to completely eliminate the PWM switching for that par-
ticular cycle. The allowable minimum pulsewidth for any of the
six PWM outputs that can be produced by the PWM controller
may be programmed using the 10-bit PWMPD register. The
minimum pulsewidth, TMIN, is programmed in increments of
tCK as:
T
PWMPD
t
MIN
CK
=×
so that a PWMPD value of 0x00A defines a permissible mini-
mum on time of 0.39
s for a 26 MHz CLKOUT. The opera-
tion of the minimum pulsewidth control ensures that the time
from turning ON to turning OFF (or alternatively from turning
OFF to turning ON) any PWM signal is never less than the
TMIN value as specified by the PWMPD register. If the PWM
controller detects that the time between turning ON and turning
OFF any one PWM signal (say AH) is less than TMIN, the PWM
pulse is deleted and the PWM signal remains completely OFF
over the PWM period. The complementary signal, AL in this
case, is then turned completely ON.
Effective PWM Resolution
In single update mode, the same values of PWMCHA, PWMCHB
and PWMCHC are used to define the on-times in both half
cycles of the PWM period. As a result, the effective resolution of
the PWM generation process is 2tCK (or 77 ns for a 26 MHz
CLKOUT), since incrementing one of the duty cycle registers
by one changes the resultant on-time of the associated PWM
signals by tCK in each half period (or 2tCK for the full period). In
double update mode, improved resolution is possible since
different values of the duty cycles registers are used to define the
on-times in both the first and second halves of the PWM period.
As a result, it is possible to adjust the on-time over the whole
period in increments of tCK. This corresponds to an effective
PWM resolution of tCK in double update mode (or 38.5 ns for a
26 MHz CLKOUT). The achievable PWM switching frequency
at a given PWM resolution is tabulated in Table IV.
Table IV. Achievable PWM Resolution in Single and Double
Update Modes (CLKOUT = 26 MHz)
Resolution
Single Update Mode
Double Update Mode
(Bits)
PWM Frequency (kHz)
8
50.8
102
9
25.4
50.8
10
12.7
25.4
11
6.35
12.7
12
3.17
6.35
OUTPUT CONTROL UNIT, PWMSEG REGISTER
The operation of the Output Control Unit is controlled by the
9-bit read/write PWMSEG register which controls two distinct
features that are directly useful in the control of ECM or BDCM.
Crossover Feature
The PWMSEG register contains three crossover bits; one for
each pair of PWM outputs. Setting Bit 8 of the PWMSEG regis-
ter enables the crossover mode for the AH/AL pair of PWM
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