參數(shù)資料
型號： ADE7878ACPZ-RL
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind
中文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40
文件頁數(shù)： 84/96頁
文件大?。?/td> 1096K
代理商： ADE7878ACPZ-RL
ADE7854/ADE7858/ADE7868/ADE7878
Rev. E| Page 85 of 96
Bit
Location
Bit Mnemonic
Default Value
Description
14
VSPHASE[2]
0
When this bit is set to 1, Phase C voltage generates Bit16 (SAG) in the STATUS1 register.
15
Reserved
0
Reserved. This bit is always 0.
Table 42. PHNOLOAD Register (Address 0xE608)
Bit
Location
Bit Mnemonic
Default Value
Description
0
NLPHASE[0]
0
0: Phase A is out of no load condition based on total active/reactive powers.
1: Phase A is in no load condition based on total active/reactive powers. Bit set together with
Bit 0 (NLOAD) in the STATUS1 register.
The ADE7854 no load condition is based only on the total active powers.
1
NLPHASE[1]
0
0: Phase B is out of no load condition based on total active/reactive powers.
1: Phase B is in no load condition based on total active/reactive powers. Bit set together with
Bit 0 (NLOAD) in the STATUS1 register.
The ADE7854 no load condition is based only on the total active powers.
2
NLPHASE[2]
0
0: Phase C is out of no load condition based on total active/reactive powers.
1: Phase C is in no load condition based on total active/reactive powers. Bit set together with
Bit 0 (NLOAD) in the STATUS1 register.
The ADE7854 no load condition is based only on the total active powers.
3
FNLPHASE[0]
0
0: Phase A is out of no load condition based on fundamental active/reactive powers. This bit
is always 0 for ADE7854, ADE7858, and ADE7868.
1: Phase A is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
4
FNLPHASE[1]
0
0: Phase B is out of no load condition based on fundamental active/reactive powers. This bit
is always 0 for ADE7854, ADE7858, and ADE7868.
1: Phase B is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
5
FNLPHASE[2]
0
0: Phase C is out of no load condition based on fundamental active/reactive powers. This bit
is always 0 for ADE7854, ADE7858, and ADE7868.
1: Phase C is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
6
VANLPHASE[0]
0
0: Phase A is out of no load condition based on apparent power.
1: Phase A is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
7
VANLPHASE[1]
0
0: Phase B is out of no load condition based on apparent power.
1: Phase B is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
8
VANLPHASE[2]
0
0: Phase C is out of no load condition based on apparent power.
1: Phase C is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
15:9
Reserved
000 0000
Reserved. These bits are always 0.
Table 43. COMPMODE Register (Address 0xE60E)
Bit
Location
Bit Mnemonic
Default Value
Description
0
TERMSEL1[0]
1
Setting all TERMSEL1[2:0] to 1 signifies the sum of all three phases is included in the CF1
output. Phase A is included in the CF1 outputs calculations.
1
TERMSEL1[1]
1
Phase B is included in the CF1 outputs calculations.
2
TERMSEL1[2]
1
Phase C is included in the CF1 outputs calculations.
3
TERMSEL2[0]
1
Setting all TERMSEL2[2:0] to 1 signifies the sum of all three phases is included in the CF2
output. Phase A is included in the CF2 outputs calculations.
4
TERMSEL2[1]
1
Phase B is included in the CF2 outputs calculations.
5
TERMSEL2[2]
1
Phase C is included in the CF2 outputs calculations.
6
TERMSEL3[0]
1
Setting all TERMSEL3[2:0] to 1 signifies the sum of all three phases is included in the CF3
output. Phase A is included in the CF3 outputs calculations.
7
TERMSEL3[1]
1
Phase B is included in the CF3 outputs calculations.
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