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參數(shù)資料
| 型號： | ADE7878ACPZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40 |
| 文件頁數(shù)： | 31/96頁 |
| 文件大?。?/td> | 1096K |
| 代理商： | ADE7878ACPZ-RL |
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ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 37 of 96
Overvoltage and Overcurrent Level Set
The content of the overvoltage (OVLVL), and overcurrent,
(OILVL) 24-bit unsigned registers is compared to the absolute
value of the voltage and current channels. The maximum value of
these registers is the maximum value of the HPF outputs:
+5,928,256 (0x5A7540). When the OVLVL or OILVL register is
equal to this value, the overvoltage or overcurrent conditions
are never detected. Writing 0x0 to these registers signifies the
overvoltage or overcurrent conditions are continuously detected,
and the corresponding interrupts are permanently triggered.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE78xx work on 32-, 16-, or 8-bit words.
Similar to the register presented in Figure 34, OILVL and
OVLVL registers are accessed as 32-bit registers with the eight
MSBs padded with 0s.
Neutral Current Mismatch—ADE7868, ADE7878
Neutral current mismatch is available in the ADE7868 and
ADE7878 only. In 3-phase systems, the neutral current is equal
to the algebraic sum of the phase currents
IN(t) = IA(t) + IB(t) + IC(t)
If there is a mismatch between these two quantities, then a
tamper situation may have occurred in the system.
The ADE7868/ADE7878 compute the sum of the phase
currents adding the content of the IAWV, IBWV, and ICWV
registers, and storing the result into the ISUM 28-bit signed
register: ISUM(t) = IA(t) + IB(t) + IC(t). ISUM is computed every
125 μs (8 kHz frequency), the rate at which the current samples
are available, and Bit 17 (DREADY) in the STATUS0 register is
used to signal when the ISUM register can be read. See the
Digital Signal Processor section for more details on Bit DREADY.
To recover ISUM(t) value from the ISUM register, use the
following expression:
FS
MAX
SUM
I
ADC
ISUM[27:0]
t
I
×
=
)
(
where:
ADCMAX = 5,928,256, the ADC output when the input is at full
scale.
IFS is the full-scale ADC phase current.
The ADE7868/ADE7878 compute the difference between the
absolute values of ISUM and the neutral current from the
INWV register, take its absolute value and compare it against
the ISUMLVL threshold. If
ISUMLVL
INWV
ISUM
≤
,
then it is assumed that the neutral current is equal to the sum
of the phase currents, and the system functions correctly. If
ISUMLVL
INWV
ISUM
>
, then a tamper situation may
have occurred, and Bit 20 (MISMTCH) in the STATUS1 register
is set to 1. An interrupt attached to the flag can be enabled by
setting Bit 20 (MISMTCH) in the MASK1 register. If enabled,
the IRQ1 pin is set low when Status Bit MISMTCH is set to 1.
The status bit is cleared and the IRQ1 pin is set back to high by
writing to the STATUS1 register with Bit 20 (MISMTCH) set to 1.
If
ISUMLVL
INWV
ISUM
≤
, then
MISMTCH = 0
If
ISUMLVL
INWV
ISUM
>
, then
MISMTCH = 1
ISUMLVL, the positive threshold used in the process, is a 24-bit
signed register. Because it is used in a comparison with an
absolute value, always set ISUMLVL as a positive number,
somewhere between 0x00000 and 0x7FFFFF. ISUMLVL uses
the same scale of the current ADCs outputs, so writing
+5,928,256 (0x5A7540) to the ISUMLVL register puts the
mismatch detection level at full scale; see the Current Channel
ADC section for details. Writing 0x000000, the default value, or
a negative value, signifies the MISMTCH event is always triggered.
The right value for the application should be written into the
ISUMLVL register after power-up or after a hardware/software
reset to avoid continuously triggering MISMTCH events.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7868/ADE7878 work on 32-, 16-, or 8-bit
words and the DSP works on 28 bits. As presented in Figure 51,
ISUM, the 28-bit signed register, is accessed as a 32-bit register
with the four most significant bits padded with 0s.
31
28 27
BIT 27 IS A SIGN BIT
0
28-BIT SIGNED NUMBER
0000
08
510
-25
0
Figure 51. The ISUM[27:0] Register is Transmitted As a 32-Bit Word
Similar to the registers presented in Figure 33, the ISUMLVL
register is accessed as a 32-bit register with four most significant
bits padded with 0s and sign extended to 28 bits.
PHASE COMPENSATION
As described in the Current Channel ADC and Voltage Channel
ADC sections, the datapath for both current and voltages is the
same. The phase error between current and voltage signals
introduced by the ADE7854/ADE7858/ADE7868/ADE7878 is
negligible. However, the ADE7854/ADE7858/ADE7868/ADE7878
must work with transducers that may have inherent phase
errors. For example, a current transformer (CT) with a phase
error of 0.1° to 3° is not uncommon. These phase errors can
vary from part to part, and they must be corrected to perform
accurate power calculations.
The errors associated with phase mismatch are particularly
noticeable at low power factors. The ADE78xx provides a means
of digitally calibrating these small phase errors. The ADE78xx
allows a small time delay or time advance to be introduced into
the signal processing chain to compensate for the small phase
errors.
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