參數(shù)資料
型號(hào)： ADE7878ACPZ-RL
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind
中文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40
文件頁(yè)數(shù)： 64/96頁(yè)
文件大?。?/td> 1096K
代理商： ADE7878ACPZ-RL
ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 67 of 96
I2C Read Operation
The read operation using the I2C interface of the ADE7854/
ADE7858/ADE7868/ADE7878 is accomplished in two stages.
The first stage sets the pointer to the address of the register. The
second stage reads the content of the register.
As seen in Figure 82, the first stage initiates when the master
generates a start condition and consists in one byte representing
the address of the ADE7854/ADE7858/ADE7868/ADE7878
followed by the 16-bit address of the target register. The ADE78xx
acknowledges every byte received. The address byte is similar to
the address byte of a write operation and is equal to 0x70 (see
the I2C Write Operation section for details). After the last byte
of the register address has been sent and acknowledged by the
ADE7854/ADE7858/ADE7868/ADE7878, the second stage
begins with the master generating a new start condition followed
by an address byte. The most significant seven bits of this address
byte constitute the address of the ADE78xx, and they are equal
to 0111000b. Bit 0 of the address byte is a read/write bit. Because
this is a read operation, it must be set to 1; thus, the first byte of
the read operation is 0x71. After this byte is received, the ADE78xx
generates an acknowledge. Then, the ADE78xx sends the value
of the register, and after every eight bits are received, the master
generates an acknowledge. All the bytes are sent with the most
significant bit first. Because registers can have 8, 16, or 32 bits,
after the last bit of the register is received, the master does not
acknowledge the transfer but generates a stop condition.
ACKNOWLEDGE
GENERATED BY
ADE78xx
ACKNOWLEDGE
GENERATED BY
MASTER
ST
A
R
T
S
A
C
K
A
C
K
A
C
K
0
15
SLAVE ADDRESS
MSB 8 BITS OF
REGISTER ADDRESS
LSB 8 BITS OF
REGISTER ADDRESS
87
0
111 0000
S
T
ART
ST
O
P
S
A
C
K
A
C
K
A
C
K
A
C
K
S
0
SLAVE ADDRESS
BYTE 3 (MSB)
OF REGISTER
BYTE 2 OF
REGISTER
BYTE 1 OF
REGISTER
BYTE 0 (LSB)
OF REGISTER
31
16
15
8
7
0
7
111 000 1
ACKNOWLEDGE
GENERATED BY
ADE78xx
N
O
A
C
K
08
51
0-
0
60
Figure 82. I2C Read Operation of a 32-Bit Register
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