參數(shù)資料
型號： ADE7878ACPZ-RL
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind
中文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40
文件頁數(shù)： 74/96頁
文件大?。?/td> 1096K
代理商： ADE7878ACPZ-RL
ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 76 of 96
Address
Register
Name
Default
Value
Description
0x43A3
AFVARGAIN
R/W
24
32 ZPSE
S
0x000000
Phase A fundamental reactive power gain
adjust (ADE7878 only).
0x43A4
AFVAROS
R/W
24
32 ZPSE
S
0x000000
Phase A fundamental reactive power
offset adjust (ADE7878 only).
0x43A5
BFVARGAIN
R/W
24
32 ZPSE
S
0x000000
Phase B fundamental reactive power gain
adjust (ADE7878 only).
0x43A6
BFVAROS
R/W
24
32 ZPSE
S
0x000000
Phase B fundamental reactive power
offset adjust (ADE7878 only).
0x43A7
CFVARGAIN,
R/W
24
32 ZPSE
S
0x000000
Phase C fundamental reactive power gain
adjust (ADE7878 only).
0x43A8
CFVAROS
R/W
24
32 ZPSE
S
0x000000
Phase C fundamental reactive power
offset adjust (ADE7878 only).
0x43A9
VATHR1
R/W
24
32 ZP
U
0x000000
Most significant 24 bits of VATHR[47:0]
threshold used in phase apparent power
datapath.
0x43AA
VATHR0
R/W
24
32 ZP
U
0x000000
Less significant 24 bits of VATHR[47:0]
threshold used in phase apparent power
datapath.
0x43AB
WTHR1
R/W
24
32 ZP
U
0x000000
Most significant 24 bits of WTHR[47:0]
threshold used in phase total/fundamental
active power datapath.
0x43AC
WTHR0
R/W
24
32 ZP
U
0x000000
Less significant 24 bits of WTHR[47:0]
threshold used in phase total/fundamental
active power datapath.
0x43AD
VARTHR1
R/W
24
32 ZP
U
0x000000
Most significant 24 bits of VARTHR[47:0]
threshold used in phase total/fundamental
reactive power datapath (ADE7858,
ADE7868, ADE7878 only).
0x43AE
VARTHR0
R/W
24
32 ZP
U
0x000000
Less significant 24 bits of VARTHR[47:0]
threshold used in phase total/fundamental
reactive power datapath (ADE7858,
ADE7868, ADE7878 only).
0x43AF
Reserved
0x000000
This memory location should be kept at
0x000000 for proper operation.
0x43B0
VANOLOAD
R/W
24
32 ZPSE
S
0x0000000
No load threshold in the apparent power
datapath.
0x43B1
APNOLOAD
R/W
24
32 ZPSE
S
0x0000000
No load threshold in the total/fundamental
active power datapath.
0x43B2
VARNOLOAD
R/W
24
32 ZPSE
S
0x0000000
No load threshold in the total/fundamental
reactive power datapath. Location
reserved for ADE7854.
0x43B3
VLEVEL
R/W
24
32 ZPSE
S
0x000000
Register used in the algorithm that
computes the fundamental active and
reactive powers (ADE7878 only).
0x43B4
Reserved
0x000000
This location should not be written for
proper operation.
0x43B5
DICOEFF
R/W
24
32 ZPSE
S
0x0000000
Register used in the digital integrator
algorithm. If the integrator is turned on, it
must be set at 0xFF8000. In practice, it is
transmitted as 0xFFF8000.
0x43B6
HPFDIS
R/W
24
32 ZP
U
0x000000
Disables/enables the HPF in the current
datapath (see Table 34).
0x43B7
Reserved
0x000000
This memory location should be kept at
0x000000 for proper operation.
0x43B8
ISUMLVL
R/W
24
32 ZPSE
S
0x000000
Threshold used in comparison between
the sum of phase currents and the neutral
current (ADE7868 and ADE7878 only).
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