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| 型號： | ADE7878ACPZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40 |
| 文件頁數(shù)： | 17/96頁 |
| 文件大小： | 1096K |
| 代理商： | ADE7878ACPZ-RL |
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ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 24 of 96
POWER-UP PROCEDURE
POR TIMER
TURNED ON
ADE78xx
POWERED UP
ADE78xx
ENTER PSM3
MICROPROCESSOR
SETS ADE78xx
IN PSM0
MICROPROCESSOR
MAKES THE
CHOICE BETWEEN
I2C AND SPI
RSTDONE
INTERRUPT
TRIGGERED
40ms
26ms
0V
3.3V – 10%
2.0V ± 10%
ADE78xx
PSM0 READY
08
51
0-
00
9
Figure 24. Power-Up Procedure
The ADE7854/ADE7858/ADE7868/ADE7878 contain an on-
chip power supply monitor that supervises the power supply
(VDD). At power-up, until VDD reaches 2 V ± 10%, the chip is
in an inactive state. As VDD crosses this threshold, the power
supply monitor keeps the chip in this inactive state for an
additional 26 ms, allowing VDD to achieve 3.3 V 10%, the
minimum recommended supply voltage. Because the PM0 and
PM1 pins have internal pull-up resistors and the external micro-
processor keeps them high, the ADE7854/ADE7858/ADE7868/
ADE7878 always power-up in sleep mode (PSM3). Then, an
external circuit (that is, a microprocessor) sets the PM1 pin to a
low level, allowing the ADE78xx to enter normal mode (PSM0).
The passage from PSM3 mode, in which most of the internal
circuitry is turned off, to PSM0 mode, in which all functionality
is enabled, is accomplished in less than 40 ms (see Figure 24 for
details).
If PSM0 mode is the only desired power mode, the PM1 pin can
be set low permanently by using a direct connection to ground.
The PM0 pin can remain open because the internal pull-up
resistor ensures that its state is high.
When the ADE7854/ADE7858/ADE7868/ADE7878 enter PSM0
mode, the I2C port is the active serial port. If the SPI port is
used, then the SS/HSA pin must be toggled three times, high to
low. This action selects the SPI port for further use. If I2C is the
active serial port, Bit 1 (I2C_LOCK) of the CONFIG2 register
must be set to 1 to lock it in. From this moment, the ADE78xx
ignores spurious toggling of the SS/HSA pin, and an eventual
switch to use the SPI port is no longer possible. Likewise, if SPI
is the active serial port, any write to the CONFIG2 register locks
the port, at which time a switch to use the I2C port is no longer
possible. Only a power-down or by setting the RESET pin low
can the ADE7854/ADE7858/ADE7868/ADE7878 be reset to use
the I2C port. Once locked, the serial port choice is maintained
when the ADE78xx changes PSMx power modes.
Immediately after entering PSM0, the ADE7854/ADE7858/
ADE7868/ADE7878 set all registers to their default values,
including the CONFIG2 and LPOILVL registers.
The ADE7854/ADE7858/ADE7868/ADE7878 signals the end of
the transition period by triggering the IRQ1 interrupt pin low and
setting Bit 15 (RSTDONE) in the STATUS1 register to 1. This
bit is 0 during the transition period and becomes 1 when the
transition ends. The status bit is cleared and the IRQ1 pin is
returned high by writing the STATUS1 register with the corres-
ponding bit set to 1. Because the RSTDONE is an unmaskable
interrupt, Bit 15 (RSTDONE) in the STATUS1 register must be
cancelled for the IRQ1 pin to return high. It is recommended to
wait until the IRQ1 pin goes low before accessing the STATUS1
register to test the state of the RSTDONE bit. At this point, as a
good programming practice, it is also recommended to cancel
all other status flags in the STATUS1 and STATUS0 registers by
writing the corresponding bits with 1.
Initially, the DSP is in idle mode, which means it does not
execute any instruction. This is the moment to initialize all
ADE78xx registers. The last register in the queue must be
written three times to ensure the register has been initialized.
Then, enable the data memory RAM protection and write
0x0001 into the run register to start the DSP (see the Digital
Signal Processor section for details on data memory RAM
protection and the run register).
If the supply voltage, VDD, drops lower than 2 V ± 10%, the
ADE7854/ADE7858/ADE7868/ADE7878 enter an inactive state,
which means that no measurements or computations are executed.
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