參數(shù)資料
型號(hào)： ADE7878ACPZ-RL
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind
中文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40
文件頁數(shù)： 82/96頁
文件大?。?/td> 1096K
代理商： ADE7878ACPZ-RL
ADE7854/ADE7858/ADE7868/ADE7878
Rev. E| Page 83 of 96
Bit
Location
Bit Mnemonic
Default Value
Description
4
VAEHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the apparent
energy registers (AVAHR, BVAHR, or CVAHR) changes.
5
LENERGY
0
When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at the end
of an integration over an integer number of half line cycles set in the LINECYC register.
6
REVAPA
0
When this bit is set to 1, it enables an interrupt when the Phase A active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
7
REVAPB
0
When this bit is set to 1, it enables an interrupt when the Phase B active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
8
REVAPC
0
When this bit is set to 1, it enables an interrupt when the Phase C active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
9
REVPSUM1
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF1
datapath changes sign.
10
REVRPA
0
When this bit is set to 1, it enables an interrupt when the Phase A reactive power identified
by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting
this bit to1 does not have any consequence for ADE7854.
11
REVRPB
0
When this bit is set to 1, it enables an interrupt when the Phase B reactive power identified
by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting
this bit to1 does not have any consequence for ADE7854.
12
REVRPC
0
When this bit is set to 1, it enables an interrupt when the Phase C reactive power identified
by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting
this bit to1 does not have any consequence for ADE7854.
13
REVPSUM2
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF2
datapath changes sign.
14
CF1
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at the
CF1 pin, that is, an active low pulse is generated. The interrupt can be enabled even if the
CF1 output is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of
power used at the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register
(see Table 45).
15
CF2
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at CF2
pin, that is, an active low pulse is generated. The interrupt may be enabled even if the CF2
output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of power
used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register (see Table 45).
16
CF3
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF3
pin, that is, an active low pulse is generated. The interrupt may be enabled even if the CF3
output is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power
used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see Table 45).
17
DREADY
0
When this bit is set to 1, it enables an interrupt when all periodical (at 8 kHz rate) DSP
computations finish.
18
REVPSUM3
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF3
datapath changes sign.
31:19
Reserved
00 0000 0000
0000
Reserved. These bits do not manage any functionality.
Table 40. MASK1 Register (Address 0xE50B)
Bit
Location
Bit Mnemonic
Default Value
Description
0
NLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters no load
condition based on total active and reactive powers.
1
FNLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters no load
condition based on fundamental active and reactive powers. Setting this bit to 1 does not
have any consequence for ADE7854, ADE7858, and ADE7868.
2
VANLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters no load
condition based on apparent power.
3
ZXTOVA
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A voltage is
missing.
4
ZXTOVB
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B voltage is
missing.
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