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參數(shù)資料
| 型號： | ADE7878ACPZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40 |
| 文件頁數(shù)： | 19/96頁 |
| 文件大?。?/td> | 1096K |
| 代理商： | ADE7878ACPZ-RL |
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ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 26 of 96
THEORY OF OPERATION
ANALOG INPUTS
The ADE7868/ADE7878 have seven analog inputs forming current
and voltage channels. The ADE7854/ADE7858 have six analog
inputs, not offering the neutral current. The current channels
consist of four pairs of fully differential voltage inputs: IAP and
IAN, IBP and IBN, ICP and ICN, and INP and INN. These vol-
tage input pairs have a maximum differential signal of ±0.5 V. In
addition, the maximum signal level on analog inputs for the
IxP/IxN pair is ±0.5 V with respect to AGND. The maximum
common-mode signal allowed on the inputs is ±25 mV. Figure 25
presents a schematic of the input for the current channels and
their relation to the maximum common-mode voltage.
IAP, IBP,
ICP, OR INP
IAN, IBN,
ICN, OR INN
VCM
V2
V1
+500mV
VCM
V1 + V2
DIFFERENTIAL INPUT
V1 + V2 = 500mV MAX PEAK
COMMON MODE
VCM = ±25mV MAX
–500mV
08
510
-01
0
Figure 25. Maximum Input Level, Current Channels, Gain = 1
All inputs have a programmable gain amplifier (PGA) with a
possible gain selection of 1, 2, 4, 8, or 16. The gain of IA, IB, and
IC inputs is set in Bits[2:0] (PGA1[2:0]) of the gain register. For
the ADE7868 and ADE7878 only, the gain of the IN input is set
in Bits[5:3] (PGA2[2:0]) of the gain register; thus, a different gain
from the IA, IB, or IC inputs is possible. See Table 44 for details
on the gain register.
The voltage channel has three single-ended voltage inputs: VAP,
VBP, and VCP. These single-ended voltage inputs have a maximum
input voltage of ±0.5 V with respect to VN. In addition, the max-
imum signal level on analog inputs for VxP and VN is ±0.5 V
with respect to AGND. The maximum common-mode signal
allowed on the inputs is ±25 mV. Figure 26 presents a schematic
of the voltage channels inputs and their relation to the maximum
common-mode voltage.
VAP, VBP,
OR VCP
VN
VCM
V1
+500mV
VCM
V1
DIFFERENTIAL INPUT
V1 + V2 = 500mV MAX PEAK
COMMON MODE
VCM = ±25mV MAX
–500mV
08
51
0-
0
12
Figure 26. Maximum Input Level, Voltage Channels, Gain = 1
All inputs have a programmable gain with a possible gain
selection of 1, 2, 4, 8, or 16. To set the gain, use Bits[8:6]
(PGA3[2:0]) in the gain register (see Table 44).
Figure 27 shows how the gain selection from the gain register
works in both current and voltage channels.
K × VIN
GAIN
SELECTION
IxN, VN
IxP, VyP
VIN
NOTES
1. x = A, B, C, N
y = A, B, C.
08
51
0-
01
1
Figure 27. PGA in Current and Voltage Channels
ANALOG-TO-DIGITAL CONVERSION
The ADE7868/ADE7878 have seven sigma-delta (Σ-Δ) analog-
to-digital converters (ADCs), and the ADE7854/ADE7858 have
six Σ-Δ ADCs. In PSM0 mode, all ADCs are active. In PSM1
mode, only the ADCs that measure the Phase A, Phase B, and
Phase C currents are active. The ADCs that measure the neutral
current and the A, B, and C phase voltages are turned off. In
PSM2 and PSM3 modes, the ADCs are powered down to
minimize power consumption.
For simplicity, the block diagram in Figure 28 shows a first-
order Σ-Δ ADC. The converter is composed of the Σ-Δ modulator
and the digital low-pass filter.
24
DIGITAL
LOW-PASS
FILTER
R
C
+
–
CLKIN/16
INTEGRATOR
VREF
1-BIT DAC
LATCHED
COMPARATOR
ANALOG
LOW-PASS FILTER
.....10100101.....
+
–
08510-
013
Figure 28. First-Order
Σ- ADC
A Σ-Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7854/ADE7858/ADE7868/ADE7878, the
sampling clock is equal to 1.024 MHz (CLKIN/16). The 1-bit
DAC in the feedback loop is driven by the serial data stream.
The DAC output is subtracted from the input signal. If the loop
gain is high enough, the average value of the DAC output (and,
therefore, the bit stream) can approach that of the input signal
level. For any given input value in a single sampling interval, the
data from the 1-bit ADC is virtually meaningless. Only when a
large number of samples are averaged is a meaningful result
obtained. This averaging is carried out in the second part of the
ADC, the digital low-pass filter. By averaging a large number of
bits from the modulator, the low-pass filter can produce 24-bit
data-words that are proportional to the input signal level.
The Σ-Δ converter uses two techniques to achieve high resolu-
tion from what is essentially a 1-bit conversion technique. The
first is oversampling. Oversampling means that the signal is
sampled at a rate (frequency) that is many times higher than
the bandwidth of interest. For example, the sampling rate in
the ADE7854/ADE7858/ADE7868/ADE7878 is 1.024 MHz,
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