參數(shù)資料
型號(hào)： ADE7878ACPZ-RL
廠商： ANALOG DEVICES INC
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind
中文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40
文件頁(yè)數(shù)： 60/96頁(yè)
文件大小： 1096K
代理商： ADE7878ACPZ-RL
ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 63 of 96
CHECKSUM REGISTER
bi(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that form
the CRC. Bit b0 is the least significant bit, and Bit b31 is the most
significant.
The ADE7854/ADE7858/ADE7868/ADE7878 have a checksum
32-bit register, CHECKSUM, that ensures certain very important
configuration registers maintain their desired value during
Normal Power Mode PSM0.
gi, i = 0, 1, 2, …, 31 are the coefficients of the generating
polynomial defined by the IEEE802.3 standard as follows:
G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 +
x5 + x4 + x2 + x + 1
(49)
The registers covered by this register are MASK0, MASK1,
COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
CONFIG, MMODE, ACCMODE, LCYCMODE, HSDC_CFG,
and another six 8-bit reserved internal registers that always have
default values. The ADE78xx computes the cyclic redundancy
check (CRC) based on the IEEE802.3 standard. The registers
are introduced one-by-one into a linear feedback shift register
(LFSR) based generator starting with the least significant bit (as
shown in Figure 77). The 32-bit result is written in the
CHECKSUM register. After power-up or a hardware/software
reset, the CRC is computed on the default values of the registers
giving the results presented in the Table 23.
g0 = g1 = g2 = g4 = g5 = g7 = 1
g8 = g10 = g11 = g12 = g16 = g22 = g26 = g31 = 1
(50)
All of the other gi coefficients are equal to 0.
FB(j) = aj – 1 XOR b31(j – 1)
(51)
b0(j) = FB(j) AND g0
(52)
bi(j) = FB(j) AND gi XOR bi 1(j – 1), i = 1, 2, 3, ..., 31
(53)
Equation 51, Equation 52, and Equation 53 must be repeated for
j = 1, 2, …, 256. The value written into the CHECKSUM register
contains the Bit bi(256), i = 0, 1, …, 31. The value of the CRC,
after the bits from the reserved internal register have passed
through LFSR, is obtained at Step j = 48 and is presented in the
Table 23. Default Values of CHECKSUM and of Internal
Registers CRC
Part No.
Default Value of
CHECKSUM
CRC of Internal
Registers
Two different approaches can be followed in using the CHECK-
SUM register. One is to compute the CRC based on the relations
(47) to (51) and then compare the value against the CHECKSUM
register. Another is to periodically read the CHECKSUM register.
If two consecutive readings differ, it can be assumed that one of
the registers has changed value and therefore, the ADE7854,
ADE7858, ADE7868, or ADE7878 has changed configuration.
The recommended response is to initiate a hardware/software
reset that sets the values of all registers to the default, including
the reserved ones, and then reinitialize the configuration registers.
ADE7854
0x2689B124
0x3A7ABC72
ADE7858
0xD6744F93
0x3E7D0FC1
ADE7868
0x93D774E6
0x23F7C7B1
ADE7878
0x33666787
0x2D32A389
Figure 78 shows how the LFSR works. The MASK0, MASK1,
COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
CONFIG, MMODE, ACCMODE, LCYCMODE, and HSDC_CFG
registers, and the six 8-bit reserved internal registers form the
bits [a255, a254,…, a0] used by LFSR. Bit a0 is the least significant
bit of the first internal register to enter LFSR; Bit a255 is the most
significant bit of the MASK0 register, the last register to enter
LFSR. The formulas that govern LFSR are as follows:
31
0
0 15
0
15
31
255 248
240
232
224
216
70 7
0 7
0
7
0
07
0
7
40
32
24
16
8 7
MASK0 MASK1 COMPMODE
CFMODE
GAIN
INTERNAL
REGISTER
INTERNAL
REGISTER
INTERNAL
REGISTER
INTERNAL
REGISTER
INTERNAL
REGISTER
INTERNAL
REGISTER
LFSR
GENERATOR
08
51
0-
0
55
Figure 77. CHECKSUM Register Calculation
b0
LFSR
FB
g0
g1
g2
g31
b1
g3
b2
b31
a255, a254,....,a2, a1, a0
08
51
0-
0
56
Figure 78. LFSR Generator Used in CHECKSUM Register Calculation
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