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參數(shù)資料
| 型號： | ADE7878ACPZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40 |
| 文件頁數(shù)： | 20/96頁 |
| 文件大?。?/td> | 1096K |
| 代理商： | ADE7878ACPZ-RL |
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ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 27 of 96
and the bandwidth of interest is 40 Hz to 2 kHz. Oversampling
has the effect of spreading the quantization noise (noise due to
sampling) over a wider bandwidth. With the noise spread more
thinly over a wider bandwidth, the quantization noise in the band
of interest is lowered, as shown in Figure 29. However, oversam-
pling alone is not efficient enough to improve the signal-to-noise
ratio (SNR) in the band of interest. For example, an oversampling
factor of 4 is required just to increase the SNR by a mere 6 dB
(1 bit). To keep the oversampling ratio at a reasonable level, it is
possible to shape the quantization noise so that the majority of
the noise lies at the higher frequencies. In the Σ-Δ modulator,
the noise is shaped by the integrator, which has a high-pass-type
response for the quantization noise. This is the second technique
used to achieve high resolution. The result is that most of the
noise is at the higher frequencies where it can be removed by
the digital low-pass filter. This noise shaping is shown in Figure 29.
NOISE
SIGNAL
NOISE
SIGNAL
0
2 4
512
FREQUENCY (kHz)
HIGH RESOLUTION
OUTPUT FROM
DIGITAL LPF
1024
0
2 4
512
FREQUENCY (kHz)
1024
DIGITAL FILTER
SHAPED NOISE
ANTIALIAS FILTER
(RC)
SAMPLING
FREQUENCY
08
51
0-
01
4
Figure 29. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
Antialiasing Filter
Figure 28 also shows an analog low-pass filter (RC) on the input
to the ADC. This filter is placed outside the ADE7854/ADE7858/
ADE7868/ADE7878, and its role is to prevent aliasing. Aliasing
is an artifact of all sampled systems as shown in Figure 30. Aliasing
means that frequency components in the input signal to the
ADC, which are higher than half the sampling rate of the ADC,
appear in the sampled signal at a frequency below half the
sampling rate. Frequency components above half the sampling
frequency (also known as the Nyquist frequency, that is, 512 kHz)
are imaged or folded back down below 512 kHz. This happens
with all ADCs regardless of the architecture. In the example shown,
only frequencies near the sampling frequency, that is, 1.024 MHz,
move into the band of interest for metering, that is, 40 Hz to
2 kHz. To attenuate the high frequency (near 1.024 MHz) noise
and prevent the distortion of the band of interest, a low-pass
filer (LPF) must be introduced. For conventional current
sensors, it is recommended to use one RC filter with a corner
frequency of 5 kHz for the attenuation to be sufficiently high at
the sampling frequency of 1.024 MHz. The 20 dB per decade
attenuation of this filter is usually sufficient to eliminate the
effects of aliasing for conventional current sensors. However, for a
di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per
decade gain. This neutralizes the 20 dB per decade attenuation
produced by the LPF. Therefore, when using a di/dt sensor, take
care to offset the 20 dB per decade gain. One simple approach is
to cascade one additional RC filter, thereby producing a 40 dB
per decade attenuation.
ALIASING EFFECTS
SAMPLING
FREQUENCY
IMAGE
FREQUENCIES
0
2
4
512
FREQUENCY (kHz)
1024
0
851
0-
0
15
Figure 30. Aliasing Effects
ADC Transfer Function
All ADCs in the ADE7854/ADE7858/ADE7868/ADE7878 are
designed to produce the same 24-bit signed output code for the
same input signal level. With a full-scale input signal of 0.5 V
and an internal reference of 1.2 V, the ADC output code is nomi-
nally 5,928,256 (0x5A7540). The code from the ADC can vary
between 0x800000 (8,388,608) and 0x7FFFFF (+8,388,607);
this is equivalent to an input signal level of ±0.707 V. However,
for specified performance, do not exceed the nominal range of
±0.5 V; ADC performance is guaranteed only for input signals
lower than ±0.5 V.
CURRENT CHANNEL ADC
Figure 31 shows the ADC and signal processing path for
Input IA of the current channels (it is the same for IB and IC).
The ADC outputs are signed twos complement 24-bit data-
words and are available at a rate of 8 kSPS (thousand samples
per second). With the specified full-scale analog input signal
of ±0.5 V, the ADC produces its maximum output code value.
Figure 31 shows a full-scale voltage signal applied to the differ-
ential inputs (IAP and IAN). The ADC output swings between
5,928,256 (0xA58AC0) and +5,928,256 (0x5A7540). The
input, IN, corresponds to the neutral current of a 3-phase
system (available in the ADE7868 and ADE7878 only). If no
neutral line is present, connect this input to AGND. The
datapath of the neutral current is similar to the path of the
phase currents as shown in Figure 32.
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