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參數(shù)資料
| 型號： | ADE7878ACPZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40 |
| 文件頁數(shù)： | 32/96頁 |
| 文件大小： | 1096K |
| 代理商： | ADE7878ACPZ-RL |
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ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 38 of 96
(8)
The phase calibration registers (APHCAL, BPHCAL, and
CPHCAL) are 10-bit registers that can vary the time advance
in the voltage channel signal path from 374.0 μs to +61.5 μs.
Negative values written to the PHCAL registers represent a time
advance whereas positive values represent a time delay. One LSB
is equivalent to 0.976 μs of time delay or time advance (clock
rate of 1.024 MHz). With a line frequency of 60 Hz, this gives
a phase resolution of 0.0211° (360° × 60 Hz/1.024 MHz) at the
fundamental. This corresponds to a total correction range of
8.079° to +1.329° at 60 Hz. At 50 Hz, the correction range is
6.732° to +1.107° and the resolution is 0.0176° (360° × 50 Hz/
1.024 MHz).
Given a phase error of x degrees, measured using the phase
voltage as the reference, the corresponding LSBs are computed
dividing x by the phase resolution (0.0211°/LSB for 60 Hz and
0.0176°/LSB for 50 Hz). Results between 383 and +63 only are
acceptable; numbers outside this range are not accepted. If the
result is negative, the absolute value is written into the PHCAL
registers. If the result is positive, 512 is added to the result
before writing it into xPHCAL.
APHCAL,
BPHCAL, or
CPHCAL =
>
+
≤
0
,
512
_
0
,
_
x
resolution
phase
x
resolution
phase
x
Figure 53 illustrates how the phase compensation is used to remove
x = 1° phase lead in IA of the current channel from the external
current transducer (equivalent of 55.5 μs for 50 Hz systems). To
cancel the lead (1°) in the current channel of Phase A, a phase
lead must be introduced into the corresponding voltage channel.
Using Equation 8, APHCAL is 57 least significant bits, rounded
up from 56.8. The phase lead is achieved by introducing a time
delay of 55.73 μs into the Phase A current.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE785xx work on 32-, 16-, or 8-bit words.
As shown in Figure 52, APHCAL, BPHCAL, and CPHCAL
10-bit registers are accessed as 16-bit registers with the six MSBs
padded with 0s.
0000 00
15
10 9
0
xPHCAL
085
10
-0
38
Figure 52. xPHCAL Registers Communicated As 16-Bit Registers
PHASE
CALIBRATION
APHCAL = 57
ADC
PGA3
VAP
VA
VN
ADC
PGA1
IAP
IA
IAN
PHASE COMPENSATION
ACHIEVED DELAYING
IA BY 56s
50Hz
1°
VA
IA
VA
IA
08
51
0-
0
39
Figure 53. Phase Calibration on Voltage Channels
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