CF4
參數(shù)資料
型號： AD5560JSVUZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 8/68頁
文件大小： 0K
描述： IC DPS PROGRAMABLE W/DAC 64TQFP
設計資源： Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
標準包裝： 1,500
類型： 電源
應用： 自動測試設備
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP 裸露焊盤
供應商設備封裝： 64-TQFP-EP（10x10）
包裝： 帶卷 (TR)
AD5560
Data Sheet
Rev. D | Page 16 of 68
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC
CF4
CF3
CF2
CF1
CF0
DUTGND
SENSE
EXTMEASIL
GUARD/SYS_DUTGND
AGND
AVSS
AVDD
EXTMEASIH1
EXTMEASIH2
AVDD
E
X
T
F
O
RCE
1A
HCAV
SS
1A
HCAV
SS
2A
E
X
T
F
O
RCE
2A
HCAV
DD
2A
HCAV
DD
1B
E
X
T
F
O
RCE
1B
HCAV
SS
1B
HCAV
SS
2B
E
X
T
F
O
RCE
2B
HCAV
DD
2B
HCAV
DD
1C
E
X
T
F
O
RCE
1C
HC_V
SS
1C
G
PO
HCAV
DD
1A
PIN 1
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD ON TOP OF PACKAGE. EXPOSED PAD IS INTERNALLY CONNECTED TO
MOST NEGATIVE POINT, AVSS.
AD5560
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20
21 22 23 24 25 26 27 28
29 30 31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
07779-
006
BUSY
CPOL
SDO
DVCC
DGND
SCLK
SDI
CPOH/CPO
CLEN/LOAD
RCLK
TMPALM
KELALM
CLALM
RESET
HW_INH/LOAD
SYNC
MEA
SO
U
T
AV
DD
C
C3
C
C0
C
C1
C
C2
SL
A
VE_
IN
AV
SS
S
Y
S
_F
O
RCE
SYS_
SEN
SE
AG
ND
VR
EF
RE
F
G
ND
AV
SS
F
O
RCE
M
AS
T
E
R_O
UT
EXPOSED PAD ON TOP
Figure 6. TQFP_EP Pin Configuration
Table 4. TQFP_EP Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLALM
Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or
unlatched.
2
KELALM
Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either
latched or unlatched.
3
TMPALM
Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched or
unlatched.
4
CPOH/CPO
Comparator High Output (CPOH) or Window Comparator Output (CPO).
5
CPOL
Comparator Low Output.
6
BUSY
Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels.
7
SDO
Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic
purposes.
8
DVCC
Digital Supply Voltage.
9
DGND
Digital Ground Reference Point.
10
SCLK
Clock Input, Active Falling Edge.
11
SDI
Serial Data Input.
12
SYNC
Frame Sync, Active Low.
13
RCLK
Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied to
this input to drive the ramp circuitry. Tie RCLK low if it is unused.
14
RESET
Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value.
15
CLEN/LOAD
Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured
as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as
LOAD input (see the system control register, Address 0x1).
16
HW_INH/LOAD
Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow
synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system
control register, Address 0x1).
17
REFGND
Accurate Ground Reference for Applied Voltage Reference.
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