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| 型號： | AD5560JSVUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DPS PROGRAMABLE W/DAC 64TQFP |
| 設(shè)計(jì)資源： | Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 電源 |
| 應(yīng)用： | 自動測試設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD5560
Rev. D | Page 31 of 68
resistors to further optimize stability and settling time perform-
ance. The AD5560 has three compensation modes: safe mode,
autocompensation mode, and manual compensation mode, all
of which are described in more detail in the Force Amplifier
Stability section.
The range of suggested compensation capacitors allows
optimum performance for any capacitive load from 0 pF
to 160 μF using one of the modes previously listed.
Although there are four compensation input pins and five feed-
forward capacitor inputs pins, all capacitor inputs may be used
only if the user intends to drive large variations of DUT load
capacitances. If the DUT load capacitance is known and does
not change for all combinations of voltage ranges and test
conditions, then it is possible only one set of CCx and CFx
capacitors may be required.
Table 8. Suggested Compensation Capacitor Selection
Capacitor
Value
C
C0
100 pF
C
C1
100 pF
C
C2
330 pF
C
C3
3.3 nF
C
F0
4.7 nF
C
F1
22 nF
C
F2
100 nF
C
F3
470 nF
C
F4
2.2 μF
The voltage range for the CCx and CFx pins is the same as the
voltage range expected on FORCE; therefore, choice of capa-
citors should take this into account. CFx capacitors can have
10% tolerance; this extra variation directly affects settling
times, especially when measuring current in the low current
ranges. Selection of CCx should be at ≤5% tolerance.
CURRENT RANGE SELECTION
Integrated thin film resistors minimize external components
and allow easy selection of current ranges from ±5 A to
±25 mA. Using external current sense resistors, two higher
current ranges are possible: EXTFORCE1 can drive currents
up to ±1.2 A, while EXTFORCE2 is designed to drive currents
up to ±500 mA. The voltage drop across the selected sense resistor
is ±500 mV when full-scale current is flowing through it.
The measure current amplifier has two gain settings, 10 and
20. The two gain settings allow users to achieve the quoted/
specified current ranges with large or small voltage swings.
The gain of 20 setting is intended for use with a 5 V reference,
and the gain of 10 setting is for use with a 2.5 V reference. Both
combinations ensure the specified current ranges. Other
VREF/gain setting combinations should only be used to
achieve smaller current ranges. Attempting to achieve greater
current ranges than the specified ranges is outside the intended
operation of the AD5560. The maximum guaranteed voltage
across RSENSE is ±0.64 V (gain of 20) or ±0.7 V (gain of 10).
HIGH CURRENT RANGES
For currents in excess of 1200 mA, a gang mode is available
whereby multiple devices are ganged together for higher currents.
There are two methods of ganging channels together; these are
discussed in the following two sections.
Master and Slaves in Force Voltage (FV) Mode
All devices are placed in force voltage (FV) mode. One device
acts as the master device and the other devices act as slaves. By
connecting in this manner, any device can be configured as the
master. Here, the MASTER_OUT pin of the master device is
connected to the output of the force amplifier, and it feeds the
inputs of each slave force amplifier (via the SLAVE_IN pin ).
All devices are connected externally to the DUT. For current
to be shared equally, there must be good matching between
each of the paths to the DUT. Settings for DPS Register 2 are
master = 0x0000, slave = 0x0400. Clamps should be disabled in
the slave devices.
EXTMEASIL
SENSE
MASTER DPS
EXTMEASIH1
SW5-a
FIN
DAC
×1
SW5-a
SW16
RSENSE
LOCAL
FEEDBACK
SW5-b
SW6
MASTER OUT
EXTFORCE1
EXTFORCE2
SLAVE IN
R
SEN
SE
R
SEN
SE
DUT
DUTGND
EXTMEASIL
SENSE
SLAVE DPS 1
EXTMEASIH1
SW5-a
FIN
DAC
×1
×20
OR
×W
×20
OR
×W
×20
OR
×W
SW5-a
SW16
LOCAL
FEEDBACK
SW5-b
SW6
MASTER OUT
EXTFORCE1
EXTFORCE2
SLAVE IN
EXTMEASIL
SENSE
SLAVE DPS 2
EXTMEASIH1
SW5-a
FIN
DAC
ISENSE
AMP
VSENSE
AMP
ISENSE
AMP
VSENSE
AMP
ISENSE
AMP
VSENSE
AMP
×1
SW5-a
SW16
LOCAL
FEEDBACK
SW5-b
SW6
MASTER OUT
EXTFORCE1
EXTFORCE2
SLAVE IN
07779-
007
Figure 54. Simplified Block Diagram of High Current Ganging Mode
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