AV
參數(shù)資料
型號(hào)： AD5560JSVUZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 67/68頁
文件大?。?/td> 0K
描述： IC DPS PROGRAMABLE W/DAC 64TQFP
設(shè)計(jì)資源： Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
標(biāo)準(zhǔn)包裝： 1,500
類型： 電源
應(yīng)用： 自動(dòng)測(cè)試設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-TQFP-EP（10x10）
包裝： 帶卷 (TR)
AD5560
Data Sheet
Rev. D | Page 8 of 68
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SYS_FORCE
Voltage Range
AVSS
AVDD
V
Current Carrying Capability1
25
+25
mA
Leakage Current
2.5
+2.5
nA
SYS_FORCE high-Z, force amplifier inhibited.
Leakage Current Tempco1
±0.00
5
±0.025
nA/°C
Path On Resistance
35
Ω
AVDD = 16.5 V, AVSS = 16.5 V.
Pin Capacitance1
5
pF
SYS_DUTGND
Voltage Range
AVSS
AVDD
V
Path On Resistance
300
400
Ω
AVDD = 16.5 V, AVSS = 16.5 V.
CURRENT CLAMP
Clamp Accuracy
Programmed
clamp value
Programmed clamp
value + 10
% of FS
MI gain = 20, with clamp separation of 2 V, and
1 V separation from AGND/0 A.
Programmed
clamp value
Programmed clamp
value + 20
% of FS
MI gain = 10, with clamp separation of 2 V, and
1 V separation from AGND/0 A.
VCLL to VCLH1
2
V
10% of FSCR (MI gain = 20), 20% of FSCR (MI
gain = 10), restriction to prevent both clamps
activating together.
VCLL to 0 A1
1
V
5% of FSCR (MI gain = 20), 10% of FSCR (MI gain
= 10), restriction to avoid impinging on FV
before programmed level.
VCLH to 0 A1
1
V
5% of FSCR (MI gain 20), 10% of FSCR (MI gain =
10), restriction to avoid impinging on FV before
programmed level.
Clamp Activation Response Time1
20
100
μs
Measured from BUSY going low to visible
clamping.
Clamp Recovery1
2
5
μs
Measured from BUSY going low to visible
recovery.
Alarm Delay 1
50
μs
Time for CLALM to flag.
FORCE AMPLIFER
Slew Rate1
1
V/s
Fastest slew rate, controlled via serial interface.
0.312
V/s
Slowest slew rate, controlled via serial interface.
Maximum Stable Load Capacitance1
160
F
Voltage Overshoot/Undershoot1
5
%
Of programmed value (≥1 V).
SETTLING TIME (FORCE AMPLIFER)
Compensation Register 1 = 0x4880 (229 nF to
380 nF, ESR 74 to 140 mΩ)
To within 10 mV of programmed value.
FV (1200 mA EXTFORCE1 Range)1
16
25
s
3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 F, full dc load.
FV (900 mA EXTFORCE1 Range)1
18
30
s
8 V step, RDUT = 8.8 Ω, CDUT = 0.22 F, full dc
load.
FV (500 mA EXTFORCE2 Range)1
34
53
s
15 V step, RDUT = 30 Ω, CDUT = 0.22 F, full dc
load.
FV (300 mA EXTFORCE2 Range)1
25
50
s
10 V step, RDUT = 33.3 Ω, CDUT = 0.22 F, full dc load.
FV (25 mA Range)1, 3
125
180
s
20 V step, RDUT = 800 Ω, CDUT = 0.22 F, full dc load.
FV (2.5 mA Range)1, 3
300
500
s
10 V step, RDUT = 4 kΩ, CDUT = 0.22 F, full dc load.
FV (250 A Range)1, 3
300
500
s
10 V step, RDUT = 40 kΩ, CDUT = 0.22 F, full dc load.
FV (25 A Range)1, 3
400
600
s
10 V step, RDUT = 400 kΩ, CDUT = 0.22 F, full dc load.
FV (5 A Range)1, 3
20
40
s
1 V step, RDUT = 200 kΩ, CDUT = 0.22 F, full dc load.
Compensation Register 1 = 0x8880 (1.7 μF to
2.9 μF, ESR 74 to 140 mΩ)
FV (180 mA EXTFORCE1 Range)1
16
25
s
3 V step, CDUT = 2.2 F, full dc load.
FV (100 mA EXTFORCE2 Range)1
60
80
s
8 V step, CDUT = 2.2 F, full dc load.
Compensation Register 1 = 0xB880 (7.9μF to
13 μF, ESR 74 to 140 mΩ)
FV (180 mA EXTFORCE1 Range)1
55
70
s
3 V step, CDUT = 10 F, full dc load.
FV (100 mA EXTFORCE2 Range)1
210
260
s
8 V step, CDUT = 10 F, full dc load.
Compensation Register 1 = 0xC880 (13 μF to
22 μF, ESR 74 to 140 mΩ)
FV (180 mA EXTFORCE1 Range)1
65
80
s
3 V step, CDUT = 20 F, full dc load.
FV (100 mA EXTFORCE2 Range)1
310
370
s
8 V step, CDUT = 20 F, full dc load.
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