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參數(shù)資料
| 型號： | AD5560JSVUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DPS PROGRAMABLE W/DAC 64TQFP |
| 設(shè)計資源： | Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130) |
| 標準包裝： | 1,500 |
| 類型： | 電源 |
| 應(yīng)用： | 自動測試設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 帶卷 (TR) |
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AD5560
Data Sheet
Rev. D | Page 38 of 68
stability problems. This is most likely to be the case when there
are both a large CR and large RC.
The RP resistor is intended to solve this problem. Again, it is
prudent not to cancel exact pole/zero cancellation with RZ and
instead allow the zero to be 2× to 3× the frequency of the pole.
It is best to be very conservative when using RZ to cancel the
load pole. Choose a high zero frequency to avoid flat spots in
the gain curve that extend bandwidth, and be conservative when
choosing RP to create a pole. Aim to place the RZ zero at 5× the
exact cancellation frequency and the RP pole at around 2× the
exact cancellation frequency. The best solution here is to avoid
this complexity by using a high quality capacitor with low ESR.
COMPENSATION STRATEGIES
Ensuring Stability into an Unknown Capacitor Up to a
Maximum Value
If the AD5560 has to be stable in a range of load capacitance
from no load capacitance to an upper limit, then select manual
compensation mode and, in Compensation Register 2, set the
parameters according to the maximum load capacitance listed
Table 14. Suggested Compensation Settings for Load Capa-
citance Range of Unknown Value to Some Maximum Value
Capacitor
gm[1:0]
RP[2:0]
RZ[2:0]
CC[3:1]
CF[2:0]
Min
Max
0
0.22 μF
2
0
000
2
0
2.2 μF
2
0
001
3
0
10 μF
2
0
010
4
0
20 μF
2
0
011
4
0
160 μF
2
0
111
4
suggested in Table 8.
Making a circuit stable over a range of load capacitances for
no load capacitance or greater means that the circuit is over-
compensated for small load capacitances, undercompensated
for high load capacitances, or both. The previous choice settings,
along with the suggested capacitor values, is a compromise
between both. By compromising phase margin into the largest
load capacitors, the system bandwidth can be increased, which
means better performance under load current transient condi-
tions. The disadvantage is that there is more overshoot during a
large DAC step. To reduce this at the expense of settling time, it
may be desirable to temporarily switch a capacitor range 5× or
10× larger before making a large DAC step.
OPTIMIZING PERFORMANCE FOR A KNOWN
CAPACITOR USING AUTOCOMPENSATION MODE
The autocompensation mode decides what values of gmx, CCx
CFx, RZ, and RP should be chosen for good performance in a
particular capacitor. Both the capacitance and its ESR need to
be known. To avoid creating an oscillator, the capacitance should
not be overestimated and the ESR should not be underesti-
mated. Use the following steps to determine compensation
settings when using the manual compensation register (this
algorithm is what the autocompensation method is based upon):
1. Use CR (the load capacitance with a series ESR) and RC (the
ESR of that load capacitance) as inputs.
2. Assume that CR has not been overestimated and that RC has
not been underestimated. (Although, when the ESR RC is
shown to have a frequency dependence, the lowest RC that
occurs near the resonant frequency is probably a better
guide. However, do not underestimate this ESR).
a. CC0 is the suggested 100 pF.
b. CFx capacitor values are as suggested, and they extend
up to 2.2 F (CF4). For faster settling into small
capacitive loads, include smaller CFx values such as CF3
and CF2. If a capacitor is not included, then short the
corresponding CFx pin to one that is.
c. There is approximately 1 Ω of parasitic resistance, RC,
from the AD5560 to the DUT (for example, the cable);
RC = 1 Ω.
3. Select gm[1:0] = 2, CC[3:1] = 000. This makes the input stage of
the force amplifier; have gmx = 300 A/V; deselect the
compensation capacitors, CC1, CC2, CC3, so that only CC0 is
active.
4. Choose a CF[2:0] value from 0 to 4 to select the largest CFx
capacitor that is smaller than CR.
5. If CR < 100 nF, then set RZ[2:0] = 0, RP[2:0] = 0. This ends the
algorithm.
6. Calculate R0, the resistive impedance to the DUT, using the
following steps:
a. Calculate RS, the sense resistor, from the selected
current range using RS = 0.5 V/IRANGE.
b. Calculate RF, the output impedance, through the CFx
capacitor, by using
RF = 1.2 Ω + (ESR of CFx capacitor)
c. Calculate RFM, a modified version of RF, which takes
account of frequency dependent peaking, through the
CFx buffers into a large capacitive load, by using
RFM = RF/(1 + [2 × (CFx/2.2 μF)])
That is, RFM is up to 3× smaller than RF, when the
selected CFx capacitor is large compared to 2.2 μF.
Then calculate
R0 = RC + (RS ||RFM)
where RC takes its value from the assumptions in Step 2.
7. If RC > (R0/5), then the ESR is large enough to make the
DUT look resistive. Choose RZ[2:0] = 0, RP[2:0] = 0. This ends
the algorithm
8. Calculate the unity gain frequency (Fug), the ideal unity
gain frequency of the force amplifier, from Fug =
gmx/2πCC0. Using the previously suggested values (gm[1:0] = 2
gives gmx = 300 A/V and CC0 = 100 pF), Fug calculates to
480 kHz.
9. Calculate FP, the load pole frequency, using FP =
1/(2πR0CC0).
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