參數(shù)資料
型號(hào)： AD5560JSVUZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 35/68頁(yè)
文件大?。?/td> 0K
描述： IC DPS PROGRAMABLE W/DAC 64TQFP
設(shè)計(jì)資源： Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
標(biāo)準(zhǔn)包裝： 1,500
類型： 電源
應(yīng)用： 自動(dòng)測(cè)試設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-TQFP-EP（10x10）
包裝： 帶卷 (TR)
AD5560
Data Sheet
Rev. D | Page 40 of 68
The transfer function for these 16-bit DACs is
DUTGND
CODE
DAC
OFFSET
V
CODE
DAC
V
VCLL
VCLH
REF
+
×
×
=
16
2
_
125
.
5
2
125
.
5
,
The transfer function for the clamp current value is
GAIN
AMP
MI
R
CODE
DAC
V
ICLH
ICLL
SENSE
REF
_
2
32768
125
.
5
,
16
×
×
=
where:
RSENSE is the sense resistor.
MI_AMP_GAIN is the gain of the MI amp (either 10 or 20).
OSD DAC
The OSD DAC is a 16-bit DAC function, again a resistor string
DAC guaranteeing monotonicity. The 16-bit binary digital
code loaded to the DAC register determines at what node on
the string the voltage is tapped off before being fed to the
output amplifier. The OSD function is used to program the
voltage difference needed between the force and sense lines
before the alarm circuit flags an error. The OSD DAC has a
range of 0.62 V to 5 V. The transfer function is as follows:
×
16
2
CODE
DAC
VREF
V
OUT
(1)
The offset DAC does not affect the OSD DAC output range.
DUTGND DAC
Similarly, the DUTGND DAC (DGS) is a 16-bit DAC and uses
a resistor string DAC to guarantee monotonicity. The 16-bit
binary digital code loaded to the DAC register determines at
what node on the string the voltage is tapped off before being
fed to the output amplifier. This function is used to program
the voltage difference needed between the DUTGND and
AGND lines before the alarm circuit flags an error.
The DUTGND DAC has a range of 0 V to 5 V. The transfer
function for this 16-bit DAC is shown in Equation 1.
The offset DAC does not affect the OSD DAC output range.
OFFSET DAC
In addition to the offset and gain trim, there is also a 16-bit
offset DAC that offsets the output of each DAC on chip. There-
fore, depending on headroom available, the input to the force
amplifier can be arranged either symmetrically or asymmetrically
about DUTGND but always within a voltage span of 25 V. Some
extra gain is included to allow for system error correction using
the m (gain) and c (offset) registers.
The usable voltage range is 22 V to +25 V. Full scale loaded
to the offset DAC does not give a useful output voltage range
because the output amplifiers are limited by available footroom.
Table 15 shows the effect of the offset DAC on other DACs in
the device (clamp, comparator, and force DACs).
Table 15. Offset DAC Relationship with Other DACs, VREF = 5 V
Offset DAC Code
DAC Code1
DAC Output Voltage Range
0
0.00
0
32,768
12.81
0
65,535
25.62
…
32,768
0
12.81
32,768
0.00
32,768
65,535
12.81
…
57,344
0
22.42
57,344
32,768
9.61
57,344
65,535
3.20
…
65,355
…
Footroom limitations
1 DAC code shown for 16-bit force DAC.
OFFSET AND GAIN REGISTERS
Each DAC level contains independent offset and gain control
registers that allow the user to digitally trim offset and gain.
These registers give the user the ability to calibrate out errors
in the complete signal chain (including the DAC) using the
internal m and c registers, which hold the correction factors.
The digital input transfer function for the DACs can be
represented as
x2 = [x1 × (m + 1)/2n] + (c – 2n – 1)
where:
x2 is the data-word loaded to the resistor string DAC.
x1 is the 16-bit data-word written to the DAC input register.
m is the code in the gain register (default code = 216 – 1).
n is the DAC resolution (n = 16).
c is the code in the offset register (default code = 215).
Offset and Gain Registers for the Force Amplifier DAC
The force amplifier input (FIN) DAC level contains independent
offset and gain control registers that allow the user to digitally
trim offset and gain. There is one set of registers for the force
voltage range: x1, m, and c.
Offset and Gain Registers for the Comparator DACs
The comparator DAC levels contain independent offset and
gain control registers that allow the user to digitally trim offset
and gain. There are seven sets of registers consisting of a combi-
nation of x1, m, and c, one set each for the five internal force
current ranges and one set each for the two external high
current ranges.
Offset and Gain Registers for the Clamp DACs
The clamp DAC levels contain independent offset and gain
control registers that allow the user to digitally trim offset
and gain. One set of registers covers the VSENSE range, the five
internal force current ranges, and the two external high current
ranges. Both clamp DAC x1 registers and their associated offset
and gain registers are 16 bit.
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