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參數(shù)資料
| 型號： | AD5560JSVUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/68頁 |
| 文件大小： | 0K |
| 描述： | IC DPS PROGRAMABLE W/DAC 64TQFP |
| 設(shè)計資源： | Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 電源 |
| 應(yīng)用： | 自動測試設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD5560
Rev. D | Page 19 of 68
Pin No.
Mnemonic
Description
D1
TMPALM
Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched
or unlatched.
D2
CPOH/CPO
Comparator High Output (CPOH) or Window Comparator Output (CPO).
D3
CPOL
Comparator Low Output.
D7
EXTMEASIH2
Input High Measure Line for External High Current Range 2.
D8
EXTMEASIH1
Input High Measure Line for External High Current Range 1.
D9,H3, J8
AVDD
Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
E1
BUSY
Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels.
E2
SDO
Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic
purposes.
E3
DVCC
Digital Supply Voltage.
E7
GUARD/SYS_DUTGND
Guard Amplifier Output Pin or
System Device Under Test Ground Pin. See the DPS Register 2 in Table 19
for addressing details.
E8
AGND
Analog Ground.
E9, G4, J4
AVSS
Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
F1
DGND
Digital Ground Reference Point.
F2
SCLK
Clock Input, Active Falling Edge.
F3
SDI
Serial Data Input.
F7
SENSE
Input Sense Line.
F8
EXTMEASIL
Low Side Measure Current Line for External High Current Ranges.
F9
DUTGND
Device Under Test Ground.
G1
SYNC
Frame Sync, Active Low.
G2
RCLK
Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied
to this input to drive the ramp circuitry. Tie RCLK low if it is unused.
G3
RESET
Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value.
G5
CC0
Compensation Capacitor Input 0.
G6
SYS_SENSE
External Sense Signal Output.
G7
SYS_FORCE
External Force Signal Input.
G8
CF2
Feedforward Capacitor 2.
G9
CF0
Feedforward Capacitor 0.
H1
CLEN/LOAD
Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured
as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as
LOAD input (see the system control register, Address 0x1).
H2
VREF
Reference Input for DAC Channels, Input Range is 2 V to 5 V.
H4
MEASOUT
Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND.
H5
CC1
Compensation Capacitor Input 1.
H6
MASTER_OUT
Master Output When Ganging Multiple DPS Devices.
H7
SLAVE_IN
Slave Input When Ganging Multiple DPS Devices.
H8
CF3
Feedforward Capacitor 3.
H9
CF1
Feedforward Capacitor 1.
J1
HW_INH/LOAD
Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow
synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system
control register, Address 0x1).
J2
REFGND
Accurate Ground Reference for Applied Voltage Reference.
J3
AGND
Analog Ground.
J5
CC3
Compensation Capacitor Input 3.
J6
CC2
Compensation Capacitor Input 2.
J7
FORCE
Output Force Pin for Internal Current Ranges.
J9
CF4
Feedforward Capacitor 4.
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