參數(shù)資料
型號(hào)： AD5560JSVUZ-REEL
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 58/68頁(yè)
文件大?。?/td> 0K
描述： IC DPS PROGRAMABLE W/DAC 64TQFP
設(shè)計(jì)資源： Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
標(biāo)準(zhǔn)包裝： 1,500
類(lèi)型： 電源
應(yīng)用： 自動(dòng)測(cè)試設(shè)備
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-TQFP-EP（10x10）
包裝： 帶卷 (TR)
Data Sheet
AD5560
Rev. D | Page 61 of 68
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consid-
eration of the power supply and ground return layout helps
to ensure the rated performance. The printed circuit board
on which the AD5560 is mounted should be designed so that
the analog and digital sections are separated and confined to
certain areas of the board. If the AD5560 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
The DGND connection in the AD5560 should be treated as
AGND and returned to the AGND plane. For more detail on
decoupling for mixed signal applications, refer to Analog
For supplies with multiple pins (AVSS, AVDD, DVCC), it is
recommended to tie these pins together and to decouple
each supply once.
The AD5560 should have ample supply decoupling of 10 F
in parallel with 0.1 F on each supply located as close to the
part as possible, ideally right up against the device. The 10 F
capacitors are the tantalum bead type. The 0.1 F capacitor
should have low effective series resistance (ESR) and effective
series inductance (ESL), such as the common ceramic capaci-
tors that provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
Digital lines running under the device should be avoided because
these couple noise onto the device. The analog ground plane
should be allowed to run under the AD5560 to avoid noise
coupling. The power supply lines of the AD5560 should use as
large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line. Fast
switching digital signals should be shielded with digital ground
to avoid radiating noise to other parts of the board and should
never be run near the reference inputs. It is essential to
minimize noise on all VREF lines. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects
of feedthrough throughout the board. As is the case for all thin
packages, care must be taken to avoid flexing the package and
to avoid a point load on the surface of this package during the
assembly process.
Also note that the exposed paddle of the AD5560 is internally
connected to the negative supply AVSS.
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