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參數(shù)資料
| 型號： | AD5560JSVUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 53/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DPS PROGRAMABLE W/DAC 64TQFP |
| 設(shè)計資源： | Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130) |
| 標準包裝： | 1,500 |
| 類型： | 電源 |
| 應用： | 自動測試設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應商設(shè)備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD5560
Rev. D | Page 57 of 68
READBACK MODE
The AD5560 allows data readback via the serial interface from
every register directly accessible to the serial interface, which is
all registers except the DAC register (x2 calibrated register). To
read back contents of a register, it is necessary to write a 1 to
the R/W bit, address the appropriate register, and fill the data
bits with all zeros.
After the write command has been written, data from the
selected register is loaded to the internal shift register and is
available on the SDO pin during the next SPI operation.
Address 0x43 and Address 0x44 are the only registers that are
read only. The read function gives the user details of the alarm
status and the comparator output result.
Alarm flags on latched alarm pins (Pin 1, Pin 2, Pin 3) and bits
are cleared after a read command of Register 0x44 (alarm status
and clear alarm register (see Table 25)).
SCLK frequency for readback does not operate at the full speed
of the SPI interface. See the Timing Characteristics section for
further details.
DAC READBACK
The DAC x1, DAC m, and DAC c registers are available to read
back via the serial interface. Access to the calibrated x2 register
is not available.
POWER-ON DEFAULT
During power-on, the power-on state machine resets all internal
registers to their default values, and BUSY goes low. A rising
edge on BUSY indicates that the power-on event is complete
and that the interface is enabled. The RESET pin has no
function in the power-on event.
During power-on, all DAC x1 registers corresponding to 0 V
are cleared; the calibration register default corresponds to m at
full scale and to c at zero scale.
The default conditions of the DPS and the system control
registers are as shown in the relevant tables (see Table 17
through Table 26).
During a RESET function, all registers are reset to the power-on
default.
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