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參數(shù)資料
| 型號(hào)： | 82C836A-20 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁數(shù)： | 152/205頁 |
| 文件大?。?/td> | 3878K |
| 代理商： | 82C836A-20 |
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The 80387sx coprocessor monitors -ADS, -READY, and CPU address bit 23 directly to
detect I/O operations addressed to it. The coprocessor operates roughly as a 16-bit data
resource except as follows:
1.
In all cases, coprocessor data is exchanged on the CPU local data bus, not on the AT
bus. -IOCS16 is not asserted.
If no coprocessor is present, attempted coprocessor I/O accesses result in bus convert
cycles, including ALE and command on the AT bus, but the data bus drivers in the
82C836 remain tristated. This allows plenty of time for the floating CPU data bus to
stablize to a valid state (a stable data bus is important for compatibility with certain
older software products that rely on attempted coprocessor I/O operations to detect
coprocessor presence or absence).
If a coprocessor is present, but the 82C836 has been programmed to generate -READY
during coprocessor accesses, ALE and command are generated. The cycle follows
normal 16-bit I/O timing except as mentioned in (1) above.
If a coprocessor is present and the 82C836 has been programmed to rely on the
coprocessor to generate -READY, ALE and command are not generated, and the
cycle ends as soon as the coprocessor issues -READY, which may be considerably
sooner than in (3) above. Zero wait state cycles are possible when the coprocessor
generates -READY.
2.
3.
4.
Since the coprocessor interface is tighly coupled to the CPU (rather than using an
-XIOR/-XIOW interface), the coprocessor is not accessible by add-on card bus masters.
DMA Timing
Figure 11-12 shows a DMA operation consisting of two back-to-back DMA transfers
between a memory resource and an I/O resource. The general protocol is as follows:
A DMA requestor asserts an assigned DREQ signal. The 82C836 then asserts HOLD
to the CPU.
Eventually the CPU responds with HLDA, causing AEN to be asserted on the AT bus
(externally gated with -MASTER). HLDA also causes ALE to be asserted. ALE
remains continuously asserted until HOLD is subsequently deasserted.
Some time after detecting HLDA, the 82C836 generates the DMA memory address
and issues the appripriate -DACK signal, followed by either -XIOR and -XMEMW, or
XMEMR- and -XIOW.
The address bus contains the memory address and is used by the memory resource.
The I/O resource that should respond to the DMA cycle is determined by the -DACK
signal. Other I/O resources not involved in the DMA cycle generally rely on AEN to
signify the address on the bus is not an I/O address.
I
CPU Access to AT-Bus
System Timing Relationships
11-20
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82C836B | Single-Chip 386sx AT |
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S19 | 576-BIT BIPOLAR RAM (64 X 9) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C836B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A/B | 制造商: 功能描述: 制造商:undefined 功能描述: |
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