參數(shù)資料
型號(hào): 7544
英文描述: 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL.
中文描述: 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03
文件頁(yè)數(shù): 47/54頁(yè)
文件大?。?/td> 503K
代理商: 7544
Rev.1.02 2003.06.25 page 47 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Electrical Characteristics
Table 12 Electrical characteristics (1) (V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, Ta =
20 to 85
°
C, unless otherwise noted)
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
I
OH
=
5 mA
V
CC
= 4.0 to 5.5 V
I
OH
=
1.0 mA
V
CC
= 2.2 to 5.5 V
I
OL
= 5 mA
V
CC
= 4.0 to 5.5 V
I
OL
= 1.5 mA
V
CC
= 4.0 to 5.5 V
I
OL
= 1.0 mA
V
CC
= 2.2 to 5.5 V
I
OL
= 15 mA
V
CC
= 4.0 to 5.5 V
I
OL
= 1.5 mA
V
CC
= 4.0 to 5.5 V
I
OL
= 10 mA
V
CC
= 2.2 to 5.5 V
V
I
= V
CC
(Pin floating. Pull up
transistors
off
)
V
I
= V
CC
V
I
= V
CC
V
I
= V
SS
(Pin floating. Pull up
transistors
off
)
V
I
= V
SS
V
I
= V
SS
V
I
= V
SS
(Pull up transistors
on
)
When clock stopped
V
CC
= 5.0 V, Ta = 25
°
C
V
CC
= 5.0 V, Ta = 25
°
C
Test conditions
V
CC
1.5
V
CC
1.0
2.0
1000
62.5
H
output voltage
P0
0
P0
7
, P1
0
P1
4
, P2
0
P2
5
, P3
0
P3
4
, P3
7
(
Note 1
)
L
output voltage
P1
0
P1
4
, P2
0
P2
5
L
output voltage
P0
0
P0
7
, P3
0
P3
4
, P3
7
Hysteresis
CNTR
0
, CNTR
1
, INT
0
, INT
1
(
Note 2
)
P0
0
P0
7
(
Note 3
)
Hysteresis
R
X
D, S
CLK
(
Note 2
)
______
RESET
H
input current
P0
0
P0
7
, P1
0
P1
4
, P2
0
P2
5
, P3
0
P3
4
, P3
7
input current
H
RESET
H
input current
X
IN
L
input current
P0
0
P0
7
, P1
0
P1
4
, P2
0
P2
5
, P3
0
P3
4
, P3
7
L
input current
RESET, CNV
SS
L
input current
X
IN
L
input current
P0
0
P0
7
, P3
0
P3
4
, P3
7
RAM hold voltage
Ring oscillator oscillation frequency
Oscillation stop detection circuit detection frequency
1.5
0.3
1.0
2.0
0.3
1.0
5.0
5.0
5.0
5.0
0.5
5.5
3000
187.5
V
V
V
V
V
V
V
V
V
V
V
μA
μA
μA
μA
μA
μA
mA
V
kHz
kHz
V
OH
V
OL
V
OL
V
T+
V
T
V
T+
V
T
V
T+
V
T
I
IH
I
IH
I
IH
I
IL
I
IL
I
IL
I
IL
V
RAM
R
OSC
D
OSC
0.4
0.5
0.5
4.0
4.0
0.2
2000
125
Notes 1:
P1
1
is measured when the P1
1
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is
0
.
2:
R
X
D, S
CLK
, INT
0
, and INT
1
have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to
0
(CMOS level).
3:
It is available only when operating key-on wake up.
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