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參數(shù)資料
| 型號： | 7544 |
| 英文描述： | 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL. |
| 中文描述： | 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03 |
| 文件頁數(shù)： | 29/54頁 |
| 文件大?。?/td> | 503K |
| 代理商： | 7544 |
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Rev.1.02 2003.06.25 page 29 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A-D Converter
The functional blocks of the A-D converter are described below.
[A-D conversion register] AD
The A-D conversion register is a read-only register that stores the
result of A-D conversion. Do not read out this register during an A-
D conversion.
[A-D control register] ADCON
The A-D control register controls the A-D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion comple-
tion bit. The value of this bit remains at
“
0
”
during A-D conversion,
and changes to
“
1
”
at completion of A-D conversion.
A-D conversion is started by setting this bit to
“
0
”
.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
by 256, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of ports P2
5
/AN
5
to P2
0
/AN
0
,
and inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores its result into the A-D
conversion register. When A-D conversion is completed, the con-
trol circuit sets the AD conversion completion bit and the AD
interrupt request bit to
“
1
”
. Because the comparator is constructed
linked to a capacitor, set f(X
IN
) to 500 kHz or more during A-D con-
version.
Fig. 31 Structure of A-D control register
Fig. 32 Block diagram of A-D converter
A-D control register
(ADCON : address 0034
16
, initial value: 10
16
)
b7 b0
Analog input pin selection bits
000 : P2
0
/AN
0
001 : P2
1
/AN
1
010 : P2
2
/AN
2
011 : P2
3
/AN
3
100 : P2
4
/AN
4
101 : P2
5
/AN
5
110 : Disable
111 : Disable
Disable (returns
“
0
”
when read)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Disable (returns
“
0
”
when read)
A-D control register
(Address 0034
16
)
C
A-D control circuit
Resistor ladder
V
REF
Comparator
A-D interrupt request
b7
b0
Data bus
3
10
P2
0
/AN
0
P2
1
/AN
1
P2
2
/AN
2
P2
3
/AN
3
P2
4
/AN
4
P2
5
/AN
5
(Address 0035
16
)
V
SS
A-D conversion register (low-order)
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