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Rev.1.02 2003.06.25 page 37 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 46 State transition
Stop mode
Wait mode
WIT
instruction
Oscillation stop detection circuit valid
CPUM
4
←
1
2
MISRG
1
¨
1
2
Interrupt
Interrupt
STP
instruction
WIT
instruction
Interrupt
MISRG
1
←
0
2
CPUM
3
¨
1
2
CPUM
3
←
0
2
CPUM
76
¨
10
2
CPUM
76
¨
00
2
01
2
11
2
(Note 2)
CPUM
4
¨
0
2
MISRG
1
¨
1
2
MISRG
1
¨
0
2
Reset released
State 1
Operation clock source:
f(X
IN
) (Note 1)
f(X
IN
) oscillation enabled
Ring oscillator stop
State 2
Operation clock source:
f(X
IN
) (Note 1)
f(X
IN
) oscillation enabled
Ring oscillator enabled
State 3
Operation clock source:
Ring oscillator (Note 3)
f(X
IN
) oscillation enabled
Ring oscillator enalbed
State 4
Operation clock source:
Ring oscillator (Note 3)
f(X
IN
) oscillation stop
Ring oscillator enalbed
Notes on switch of clock
(1) In operation clock source = f(X
IN
), the following can be
selected for the CPU clock division ratio.
G
f(X
IN
)/2 (high-speed mode)
G
f(X
IN
)/8 (middle-speed mode)
G
f(X
IN
) (double-speed mode, only at a ceramic/quartz-crystal
oscillation)
(2) Execute the state transition state 3 to state 2 or
state 3
’
to state 2
’
after stabilizing X
IN
oscillation.
(3) In operation clock source = ring oscillator, the middle-
speed mode is selected for the CPU clock division ratio.
(4) When the state transition state 2
→
state 3
→
state 4
is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
CPUM76
→
10
2
(State 2
→
state 3)
NOP instruction
CPUM4
→
1
2
(State 3
→
state 4)
Double-speed mode at ring oscillator: NOP
3
High-speed mode at ring oscillator: NOP
1
Reset state
CPUM
76
¨
10
2
CPUM
76
←
00
2
01
2
11
2
(Note 2)
State 2
’
Operation clock source:
f(X
IN
) (Note 1)
f(X
IN
) oscillation enabled
Ring oscillator enabled
State 3
’
Operation clock source:
Ring oscillator (Note 3)
f(X
IN
) oscillation enabled
Ring oscillator enalbed