參數(shù)資料
型號: 7544
英文描述: 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL.
中文描述: 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03
文件頁數(shù): 16/54頁
文件大?。?/td> 503K
代理商: 7544
Rev.1.02 2003.06.25 page 16 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 16 Block diagram of ports (2)
Pull-up control
INT interrupt input
P3 input level
selection bit
(10) Ports P3
0
P3
3
Pull-up control
(8) Port P1
4
Data bus
Serial I/O ready output
Port latch
Direction
register
CNTR
0
interrupt input
Pulse output mode
Timer output
Serial I/O mode selection bit
Serial I/O enable bit
S
RDY
output enable bit
P1
0
, P1
2
, P3
4
, and P3
7
input level are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
Data bus
Port latch
Direction
register
Data bus
Port latch
Direction
register
Data bus
Port latch
Direction
register
A-D converter input
Analog input pin
selection bit
(11) Ports P3
4
, P3
7
Data bus
Port latch
Direction
register
*
*
(9) Ports P2
0
P2
5
(7) Port P1
3
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