參數(shù)資料
型號(hào): 7544
英文描述: 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL.
中文描述: 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03
文件頁數(shù): 24/54頁
文件大?。?/td> 503K
代理商: 7544
Rev.1.02 2003.06.25 page 24 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 24 Block diagram of timer 1 and timer A
Timer A (low-order) latch (8)
Timer A (low-order) (8)
Timer A (high-order) latch (8)
Timer A (high-order) (8)
Data bus
P0
0
/CNTR
1
CNTR
active
edge switch bit
Rising edge detected
Falling edge detected
Timer A operation mode bit
Timer A count
stop bit
Prescaler 1 latch (8)
Prescaler 1 (8)
Timer 1 latch (8)
Timer 1 (8)
Data bus
Timer A interrupt
request bit
Timer 1 interrupt
request bit
Pulse width HL
continuously
measurement mode
Period measurement mode
f(X
IN
)/16
f(X
IN
)/2
Ring oscillator clock RING
f(X
IN
)/16
f(X
IN
)/2
Ring oscillator clock RING
Fig. 25 Block diagram of timer X
Q
Q
P1
4
/CNTR
0
R
T
f(X
IN
)/16
f(X
IN
)/2
f(X
IN
)
Timer X
interrupt
request bit
Toggle flip-flop
Timer X count stop bit
Pulse width
measurement
mode
Event
counter
mode
CNTR
0
interrupt
request bit
Pulse output mode
Port P1
4
latch
Port P1
4
direction
register
CNTR
0
active
edge switch bit
Timer mode
Pulse output
mode
CNTR
active
edge switch bit
Timer X count
P0
3
/TX
OUT
Prescaler X latch (8)
Prescaler X (8)
Timer X latch (8)
Timer X (8)
Data bus
0
1
0
1
Writing to timer X latch
P0
3
/TX
OUT
output valid
Port P0
3
latch
Port P0
3
direction
register
Pulse output mode
Timer X write control bit
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