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參數(shù)資料
| 型號： | 7544 |
| 英文描述： | 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL. |
| 中文描述： | 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03 |
| 文件頁數(shù)： | 12/54頁 |
| 文件大?。?/td> | 503K |
| 代理商： | 7544 |
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Rev.1.02 2003.06.25 page 12 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 12 Memory map of special function register (SFR)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Pull-up control register (PULL)
Transmit/Receive buffer register (TB/RB)
Serial I/O status register (SIO1STS)
Serial I/O control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Port P1P3 control register (P1P3C)
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Timer count source set register1 (TCSS1)
A-D register (AD)
Prescaler 1 (PRE1)
Timer 1 (T1)
Reserved
Timer X mode register
(TXM)
Prescaler X
(PREX)
Timer X
(TX)
Reserved
Reserved
A-D control register (ADCON)
Reserved
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register
(INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
Timer A mode register (TAM)
Timer A (low-order) (TAL)
Timer A (high-order) (TAH)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Interrupt request register 2 (IREQ2)
Interrupt control register 2 (ICON2)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Timer count source set register2 (TCSS2)
Reserved
Reserved
Reserved
Note
: Do not access to the SFR area including nothing.
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