參數(shù)資料
型號： 7544
英文描述： 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL.
中文描述： 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03
文件頁數(shù)： 39/54頁
文件大?。?/td> 503K
代理商： 7544
Rev.1.02 2003.06.25 page 39 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
NOTES ON PERIPHERAL FUNCTIONS
I
Interrupt
When setting the followings, the interrupt request bit may be set to
“
1
”
.
When setting external interrupt active edge
Related register: Interrupt edge selection register (address
003A
16
)
Timer X mode register (address 2B
16
)
Timer A mode register (address 1D
16
)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to
“
0
”
(disabled).
Set the interrupt edge select bit (active edge switch bit) to
“
1
”
.
Set the corresponding interrupt request bit to
“
0
”
after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to
“
1
”
(enabled).
I
Timers
When n (0 to 255) is written to a timer latch, the frequency divi-
sion ratio is 1/(n+1).
When a count source of timer X is switched, stop a count of timer
X.
I
Timer A
CNTR
1
interrupt active edge selection
CNTR
1
interrupt active edge depends on the CNTR
1
active edge
switch bit.
When this bit is
“
0
”
, the CNTR
1
interrupt request bit is set to
“
1
”
at
the falling edge of the CNTR
1
pin input signal. When this bit is
“
1
”
,
the CNTR
1
interrupt request bit is set to
“
1
”
at the rising edge of
the CNTR
1
pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR
1
interrupt request is generated at both rising and falling
edges of CNTR
1
pin input signal regardless of the setting of
CNTR
1
active edge switch bit.
I
Timer X
CNTR
0
interrupt active edge selection
CNTR
0
interrupt active edge depends on the CNTR
0
active edge
switch bit.
When this bit is
“
0
”
, the CNTR
0
interrupt request bit is set to
“
1
”
at
the falling edge of CNTR
0
pin input signal. When this bit is
“
1
”
, the
CNTR
0
interrupt request bit is set to
“
1
”
at the rising edge of
CNTR
0
pin input signal.
I
Serial I/O
Serial I/O interrupt
When setting the transmit enable bit to
“
1
”
, the serial I/O transmit
interrupt request bit is automatically set to
“
1
”
. When not requiring
the interrupt occurrence synchronized with the transmission en-
abled, take the following sequence.
Set the serial I/O transmit interrupt enable bit to
“
0
”
(disabled).
Set the transmit enable bit to
“
1
”
.
Set the serial I/O transmit interrupt request bit to
“
0
”
after 1 or
more instructions have been executed.
Set the serial I/O transmit interrupt enable bit to
“
1
”
(enabled).
I/O pin function when serial I/O is enabled.
The functions of P1
2
and P1
3
are switched with the setting values
of a serial I/O mode selection bit and a serial I/O synchronous
clock selection bit as follows.
(1) Serial I/O mode selection bit
→
“
1
”
:
Clock synchronous type serial I/O is selected.
Setup of a serial I/O synchronous clock selection bit
“
0
”
: P1
2
pin turns into an output pin of a synchronous clock.
“
1
”
: P1
2
pin turns into an input pin of a synchronous clock.
Setup of a SRDY output enable bit (SRDY)
“
0
”
: P1
3
pin can be used as a normal I/O pin.
“
1
”
: P1
3
pin turns into a SRDY output pin.
(2) Serial I/O mode selection bit
→
“
0
”
:
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O synchronous clock selection bit
“
0
”
: P1
2
pin can be used as a normal I/O pin.
“
1
”
: P1
2
pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P1
3
pin. It can be used as a normal I/O pin.
I
A-D Converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(X
IN
) is 500kHz or more during A-D conversion.
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