參數(shù)資料
型號(hào): 7544
英文描述: 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL.
中文描述: 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03
文件頁(yè)數(shù): 15/54頁(yè)
文件大?。?/td> 503K
代理商: 7544
Rev.1.02 2003.06.25 page 15 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 15 Block diagram of ports (1)
(6)Port P1
2
Serial I/O clock output
Serial I/O mode selection bit
Serial I/O enable bit
Sclock selection bit
Serial I/O synchronous
Direction
register
Data bus
Port latch
Serial I/O clock input
P1
0
, P1
2
input level
selection bit
*
(2)Ports P0
1
,P0
2
,P0
4
P0
7
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
(1)Port P0
0
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
CNTR
1
interrupt input
(3)Port P0
3
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
Timer output
P0
3
/TX
OUT
output valid
(5)Port P1
1
Data bus
Port latch
Serial I/O output
P1
1
/T
x
D P-channel output disable bit
Direction
register
Serial I/O enable bit
Transmit enable bit
(4)Port P1
0
Direction
register
Data bus
Port latch
Serial I/O enable bit
Receive enable bit
Serial I/O input
P1
, P1
input level
selection bit
*
*
P1
0
, P1
2
, P3
4
, and P3
7
input level are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
P0
key-on wakeup
selection bit
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