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Rev.1.02 2003.06.25 page 32 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 37 Internal status of microcomputer at reset
X : Undefined
The content of other registers is undefined when the microcomputer is reset.
The initial values must be surely set bifore you use it.
Register contents
00
16
Address
0001
16
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P3 direction register
Pull-up control register
Port P1P3 control register
Serial I/O status register
Serial I/O control register
UART control registe
Timer A mode register
Timer A (low-order)
Timer A (high-order)
Prescaler 1
Timer 1
Timer X mode register
Prescaler X
Timer X
Timer count source set register 1
Timer count source set register 2
A-D control register
MISRG
Watchdog timer control register
Interrupt edge selection register
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Processor status register
Program counter
0003
16
0005
16
0007
16
0016
16
0017
16
0019
16
001A
16
001B
16
001D
16
001E
16
001F
16
0028
16
0029
16
002B
16
002C
16
002D
16
002E
16
002F
16
0034
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
(PS) (
PC
H
)
(PC
L
)
00
16
X
X
0
0
0
0
X
0
X
X
0
0
0
0
0
0
0
X
0
0
0
0
X
0
00
16
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
00
16
FF
16
FF
16
FF
16
0
0
0
0
0
1
0
0
00
16
FF
16
FF
16
00
16
0
0
0
0
0
0
0
1
00
16
0
0
1
1
1
1
1
1
00
16
00
16
00
16
1
0
0
0
0
0
0
0
00
16
00
16
00
16
00
16
X
X
X
1
X
X
X
X
Contents of address FFFD
16
Contents of address FFFC
16