Central Processor Unit (CPU)
Technical Data
MC68HC08AZ32A — Rev 1.0
92
Central Processor Unit (CPU)
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MOTOROLA
SEI
Set Interrupt Mask
I
←
1
– – 1 – – – INH
9B
2
STA
opr
STA
opr
STA
opr
,X
STA
opr
,X
STA ,X
STA
opr
,SP
STA
opr
,SP
Store A in M
M
←
(A)
0 – –
–
DIR
EXT
IX2
IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9E
E7
9E
D7
dd
hh
ll
ee
ff
ff
ff
ee
ff
3
4
4
3
2
4
5
STHX
opr
Store H:X in M
(M:M + 1)
←
(H:X)
0 – –
– DIR
35
dd
4
STOP
Enable IRQ Pin; Stop Oscillator
I
←
0; Stop Oscillator
– – 0 – – – INH
8E
1
STX
opr
STX
opr
STX
opr
,X
STX
opr
,X
STX ,X
STX
opr
,SP
STX
opr
,SP
Store X in M
M
←
(X)
0 – –
–
DIR
EXT
IX2
IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9E
EF
9E
DF
dd
hh
ll
ee
ff
ff
ff
ee
ff
3
4
4
3
2
4
5
SUB #
opr
SUB
opr
SUB
opr
SUB
opr
,X
SUB
opr
,X
SUB ,X
SUB
opr
,SP
SUB
opr
,SP
Subtract
A
←
(A)
–
(M)
– –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9E
E0
9E
D0
ii
dd
hh
ll
ee
ff
ff
ff
ee
ff
2
3
4
4
3
2
4
5
SWI
Software Interrupt
PC
←
(PC) + 1; Push (PCL)
SP
←
(SP) – 1; Push (PCH)
SP
←
(SP) – 1; Push (X)
SP
←
(SP) – 1; Push (A)
SP
←
(SP) – 1; Push (CCR)
SP
←
(SP) – 1; I
←
1
PCH
←
Interrupt Vector High Byte
PCL
←
Interrupt Vector Low Byte
– – 1 – – – INH
83
9
TAP
Transfer A to CCR
CCR
←
(A)
INH
84
2
TAX
Transfer A to X
X
←
(A)
– – – – – – INH
97
1
TPA
Transfer CCR to A
A
←
(CCR)
– – – – – – INH
85
1
TST
opr
TSTA
TSTX
TST
opr
,X
TST ,X
TST
opr
,SP
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0 – –
–
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E
6D
dd
ff
ff
3
1
1
3
2
4
TSX
Transfer SP to H:X
H:X
←
(SP) + 1
– – – – – – INH
95
2
Table 6-1. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
A
M
O
O
C
V H I N Z C
F
Freescale Semiconductor, Inc.
n
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